DMPRA: A Dynamic Reconfiguration Mechanism for a Dual-Mode Programmable Reconfigurable Array Architecture

Abstract

To improve the performance and power efficiency of various algorithms in specific applications, reconfigurable architecture has become an effective choice in academia and industry. However, due to the slow context updates and the insufficient flexibility, the existing reconfigurable architectures suffer from performance bottlenecks. Therefore, this paper proposed a dynamic reconfiguration mechanism applied to dual-mode programmable reconfigurable array architecture. This mechanism adopts Huffman-like coding and mask addressing, and through the H-tree transmission network, it can transmit the reconfiguration instruction/context to a specific processing element or processing element cluster in unicast, multicast, or broadcast modes within a clock cycle and shut down unnecessary processing elements or processing element clusters according to the current configuration. Meanwhile, a homogeneous reconfigurable array is designed to verify the correctness and effectiveness of the proposed dynamic reconfiguration mechanism. In this array, the processing element supports both instruction flow and data flow modes. Finally, the proposed work is implemented in register transfer level synthesis and a field-programmable gate array prototype, and its performance is verified using high-efficiency video coding algorithm. The results show that the proposed reconfiguration mechanism can effectively improve the hardware resource utilization and reconfiguration efficiency, it also can achieve the performance breakthrough of the reconfigurable architecture.