DNestMap: Mapping Deeply-Nested Loops on Ultra-Low Power CGRAs

Karunaratne, Manupa; Tan, Cheng; Kulkarni, Aditi; Mitra, Tulika; Peh, Li-Shiuan

doi:10.1109/dac.2018.8465833

Cited by 7 publications

(5 citation statements)

References 15 publications

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“…However, the traditional modulo scheduling (software pipelining) [16] for kernel mapping fails to convert nested loops and complex if-else structures to static code for CGRAs. Some software pipelining solutions or mapping techniques have been proposed to solve this problem [17], [18], but this work focuses on solutions at the architecture level.…”

Section: Related Workmentioning

confidence: 99%

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Denkinger

Peón-Quirós

Konijnenburg

et al. 2023

IEEE Trans. Comput.

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Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The latter can be divided into custom accelerators (e.g., ASICs) and programmable domain-specific cores (e.g., DSIPs). VWR2A [1] is a programmable architecture that integrates high computational density and low power memory structures. The flexibility of VWR2A allows a large portion of applications to be covered, resulting in better performance and energy efficiency than ASICs and general-purpose processors. However, while this has been well studied for data-intensive kernels, this is not the case for control-intensive kernels -code with complex if-else and nested loop structures. Traditionally, control-intensive code is left to be executed by the host processor. This situation unnecessarily restricts the potential impact of energy-efficient acceleration, especially at the application level. In this paper, we evaluate the performance and energy consumption of VWR2A for control-intensive code and compare it with an ARM Cortex-M4 processor and a RISC-V Ibex processor. The performance and energy consumption are evaluated at the kernel and application levels. Our results confirm that VWR2A is faster and more energy-efficient than the two considered general-purpose processors also for control-intensive code.

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Section: Related Workmentioning

confidence: 99%

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Denkinger

Peón-Quirós

Konijnenburg

et al. 2023

IEEE Trans. Comput.

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“…Moreover, a homogeneous interconnect handles different data types (e.g., operands and predicates) the same way when ideally they should be treated differently to save energy. Local Memory : Configuration memory takes up significant power in architectures with spatial-temporal mapping given per-cycle reconfiguration [20]. Typically the opcode, constants, and router settings are encoded into a single configuration word in a homogeneous design.…”

Section: Homogeneity Leads To Inefficiencymentioning

confidence: 99%

REVAMP: a systematic framework for heterogeneous CGRA realization

Bandara

Wijerathne

Mitra

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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Coarse-Grained Reconfigurable Architectures (CGRAs) provide an excellent balance between performance, energy efficiency, and flexibility. However, increasingly sophisticated applications, especially on the edge devices, demand even better energy efficiency for longer battery life.Most CGRAs adhere to a canonical structure where a homogeneous set of processing elements and memories communicate through a regular interconnect due to the simplicity of the design. Unfortunately, the homogeneity leads to substantial idle resources while mapping irregular applications and creates inefficiency. We plan to mitigate the inefficiency by systematically and judiciously introducing heterogeneity in CGRAs in tandem with appropriate compiler support.We propose REVAMP, an automated design space exploration framework that helps architects uncover and add pertinent heterogeneity to a diverse range of originally homogeneous CGRAs when fed with a suite of target applications. REVAMP explores a comprehensive set of optimizations encompassing compute, network, and memory heterogeneity, thereby converting a uniform CGRA into a more irregular architecture with improved energy efficiency. As CGRAs are inherently software scheduled, any micro-architectural optimizations need to be partnered with corresponding compiler support, which is challenging with heterogeneity. The REVAMP framework extends compiler support for efficient mapping of loop kernels on the derived heterogeneous CGRA architectures.We showcase REVAMP on three state-of-the-art homogeneous CGRAs, demonstrating how REVAMP derives a heterogeneous variant of each homogeneous architecture, with its corresponding compiler optimizations. Our results show that the derived heterogeneous architectures achieve up to 52.4% power reduction, 38.1% area reduction, and 36% average energy reduction over the corresponding homogeneous versions with minimal performance impact for the selected kernel suite.

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“…A solution adopted in many cases is to let the control flow managed by a host processor. But this reduces greatly the pos- Spatial mapping [23], [30], [31] GA [19] SA [32], [33] ILP [23], [34], [35] Temporal mapping [12], [16], [26], [36]- [40] SA [22] ILP [41] B&B [42] CP [43] SAT [17] SMT [44] Binding [14], [24], [28], [45]- [47] QEA [48] SA [30], [49], [50] ILP [15], [48] Scheduling [24], [28], [36], [46], [48], [50]- [52] ILP [15], [53] sibilities to use the CGRA and increases the communication overhead, loosing sometimes the benefit of the acceleration provided by the CGRA. Another approach is to provide the CGRA with extra hardware features to support the control flow.…”

Section: B Control-flow Mappingmentioning

confidence: 99%

Twenty Years of Automated Methods for Mapping Applications on CGRA

Martin

2022

2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Coarse-GrainedReconfigurable Architectures (CGRAs) emerged about 30 years ago. The very first CGRAs were programmed manually. Fortunately, some compilation approaches appeared rapidly to automate the mapping process. Numerous surveys on these architectures exist. Other surveys also gather the tools and methods, but none of them focuses on the mapping process only. This paper focuses solely on automated methods and techniques for mapping applications on CGRA and covers the last two decades of research. This paper aims at providing the terminology, the problem formulation, and a classification of existing methods. The paper ends with research challenges and trends for the future.

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DNestMap: Mapping Deeply-Nested Loops on Ultra-Low Power CGRAs

Cited by 7 publications

References 15 publications

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

REVAMP: a systematic framework for heterogeneous CGRA realization

Twenty Years of Automated Methods for Mapping Applications on CGRA

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