Domain-Specific Multi-Level IR Rewriting for GPU

Abstract

Most compilers have a single core intermediate representation (IR) (e.g., LLVM) sometimes complemented with vaguely defined IR-like data structures. This IR is commonly low-level and close to machine instructions. As a result, optimizations relying on domain-specific information are either not possible or require complex analysis to recover the missing information. In contrast, multi-level rewriting instantiates a hierarchy of dialects (IRs), lowers programs level-by-level, and performs code transformations at the most suitable level. We demonstrate the effectiveness of this approach for the weather and climate domain. In particular, we develop a prototype compiler and design stencil- and GPU-specific dialects based on a set of newly introduced design principles. We find that two domain-specific optimizations (500 lines of code) realized on top of LLVM’s extensible MLIR compiler infrastructure suffice to outperform state-of-the-art solutions. In essence, multi-level rewriting promises to herald the age of specialized compilers composed from domain- and target-specific dialects implemented on top of a shared infrastructure.

Lifting Code Generation of Cardiac Physiology Simulation to Novel Compiler Technology

“…While our overall contribution is to connect a simulating infrastructure for the study of the human heart to compiler technology, our work shows a proof-of-concept MLIR code generation that does not require an additional dialect proposal. Though this could be perceived as lacking since many previous work on MLIR [9,28,29] have proposed new dialects, we have found no justification for the addition of a new language. Indeed, MLIR includes all necessary dialects and operations required to optimize the execution of ionic models.…”

“…Gysi et al [9] propose a hierarchy of dialects (IRs) for GPU-based stencil computations that is effective in weather and climate applications. A multi-level rewriting flow is proposed to progressively lower abstractions level-by-level, applying optimizations at the most appropriate abstraction.…”

School of Mechanical Engineering, Shanghai Jiao Tong University, 200240, Shanghai, China

“…In contrast, using multiple layers of IRs to represent schedule methods streamlines the implementation process of different analysis, transformation, and optimization methods, which exhibits greater flexibility and systematicness and allows for more efficient design space exploration. Most related tools with multi-level IRs target CPUs, GPUs, and specialized processors [10], [12], [17], [26], [37]. ScaleHLS [35] proposes an HLS framework for FPGAs on top of the multi-level intermediate representation (MLIR) compiler infrastructure [23].…”

Accelerating high‐order stencils on GPUs

“…Other related work tackles stencil computations with interesting approaches, including auto‐tuning with dynamic resource allocations, 23 DAG reordering, 24 diamond tiling using a polyhedral model, 25,26 functional programming, 27,28 and multi‐layer intermediate representations 29‐31 …”