Abstract:We have developed a domino logic synthesis system with a new technology mapping algorithm based on a bin packing algorithm that reduces the levels of the circuits and considers the complexity of domino primitive cells. Domino logic circuits have 20–50% performance advantage over static circuits. By using this system, designing domino logic circuits becomes much easier than manual design. The primary reason is that logic design is completely automated by the system. The second reason is that domino primitive ce… Show more
“…These are presented in columns 6, 7 of Table. 5 respectively. The approaches Binpack [24] and CCMAP [13] are also applied on the considered benchmarks and their respective area, delay measures are shown in columns 2-5 respectively. It is clear from the analysis that approach Binpack gives better results in terms of both area and delay compared to approach in CCMAP because of heavy logic duplication deficit which occurs in the later approach.…”
Section: Resultsmentioning
confidence: 99%
“…9(a) and 9(b) respectively. [13]), P2 (Binpack, [24]), P3 (Reo_Map), P4 (Opt_Map) approaches normalized to TM Table 5. Performance evaluation of various approaches…”
Section: Resultsmentioning
confidence: 99%
“…This approach includes adding extra PMOS discharge transistors. Work [24] presents a bin packaging algorithm for library free mapping. This approach simplified the level and cell complexity.…”
Section: Introductionmentioning
confidence: 99%
“…Work mentioned in [21], can be applied to only SOI devices and not suitable for Domino circuits in general. Mapping techniques presented in [24] and [26] though emphasized on minimizing the cell complexity by reducing the levels, there was hardly any focus on minimizing overall circuit delay.…”
“…These are presented in columns 6, 7 of Table. 5 respectively. The approaches Binpack [24] and CCMAP [13] are also applied on the considered benchmarks and their respective area, delay measures are shown in columns 2-5 respectively. It is clear from the analysis that approach Binpack gives better results in terms of both area and delay compared to approach in CCMAP because of heavy logic duplication deficit which occurs in the later approach.…”
Section: Resultsmentioning
confidence: 99%
“…9(a) and 9(b) respectively. [13]), P2 (Binpack, [24]), P3 (Reo_Map), P4 (Opt_Map) approaches normalized to TM Table 5. Performance evaluation of various approaches…”
Section: Resultsmentioning
confidence: 99%
“…This approach includes adding extra PMOS discharge transistors. Work [24] presents a bin packaging algorithm for library free mapping. This approach simplified the level and cell complexity.…”
Section: Introductionmentioning
confidence: 99%
“…Work mentioned in [21], can be applied to only SOI devices and not suitable for Domino circuits in general. Mapping techniques presented in [24] and [26] though emphasized on minimizing the cell complexity by reducing the levels, there was hardly any focus on minimizing overall circuit delay.…”
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