Dopant penetration effects on polysilicon gate HfO/sub 2/ MOSFET's

Onishi, K.; Kang, Laegu; Choi, Rino; Dharmarajan, E.; Gopalan, Sundararaman; Jeon, Young‐Jin; Kang, Chang Seok; Lee, Byoung Hun; Nieh, R.; Lee, J.C.

doi:10.1109/vlsit.2001.934984

Cited by 14 publications

(14 citation statements)

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“…The extracted peak mobility value for PMOS was considerably higher with metal gates than poly-Si gate for HfO 2 gate dielectric [10], while in NMOS there was a minor improvement. This can be attributed to the severity of dopant penetration in PMOS compared to NMOS as suggested in [18]. Table 1 gives the summary of the noise parameters extracted for the devices under study.…”

Section: Resultsmentioning

confidence: 99%

Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric

Devireddy

Min

Çelik‐Butler

et al. 2007

Microelectronics Reliability

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Section: Resultsmentioning

confidence: 99%

Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric

Devireddy

Min

Çelik‐Butler

et al. 2007

Microelectronics Reliability

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“…The diffusion of common impurities such as arsenic and boron would pose a problem when poly-Si gate electrode is used with the high-k material [48]. When poly-silicon is used as the gate electrode, it must be highly doped with phosphorous and arsenic for NMOSFETs and with boron for PMOSFETs to reduce the sheet resistance of the electrode and adjust the threshold voltage.…”

Section: Compatibility With Lsi Processesmentioning

confidence: 99%

“…Kang et al [42] claimed that nitrogen incorporation at the gate dielectric/Si interface region and SiN formation may lead to the suppression of SiO formation in the reaction R3 mentioned above, resulting in the suppression of the leakage current increase. The suppression of diffusion of oxygen [42,43] as well as impurities such as boron [48,53,54] through the film has also been reported to be a beneficial influence of the nitrogen incorporation.…”

Section: Hafnium-nitrogen-based Gate Dielectricsmentioning

confidence: 99%

Hafnium-Based Gate Dielectric Materials

Nishiyama

2013

High Permittivity Gate Dielectric Materials

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In this chapter, we focus on hafnium-based gate dielectrics. HfO 2 is regarded as the most promising material for the high-k gate dielectrics owing to its large dielectric constant and large band-gap energy. In the first part of this chapter, these characteristics are addressed in a comparison with SiO 2 and other high-k materials. Thermal stability is a major issue for the application of high-k materials to MOSFETs in LSIs. Although HfO 2 satisfies this requirement, severer process conditions may cause problems even with this material. Suppression of these issues is also addressed in the second part of this chapter. In order to enhance the characteristics of HfO 2 , transformation of the monoclinic phase to the tetragonal and the cubic phases with larger dielectric constant has been pursued recently. We mention the issue in the last part of this chapter. Introductory Remarks and Brief Outline of the ChapterSince the proposal of the materials in the early 2000s [1-3], hafnium-based gate dielectrics have been regarded as the most promising materials for the application to large scale integrations (LSIs). In 2007, Intel announced the start of manufacturing of 45 nm-node LSIs with high-k/metal gate stack, with the remark that the world's first high-k material in commercial production was hafnium-based [4].There are several characteristics that the high-k materials should meet for the application to metal oxide semiconductor field effect transistors (MOSFETs) in LSIs. First, we clarify the properties so that readers can understand their A. Nishiyama

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“…There is a concern that the mobility of the channel carriers may be degraded by interactions with these soft phonons. [8][9][10][11][12][13][14][15][16][17][18] These metal oxides have reasonably high dielectric constants and band gaps (see Figure 3). Both ZrO 2 and HfO 2 devices have demonstrated a many orders of magnitude reduction in gate leakage with an EOT around 1.0 nm and well-behaved t r a n s i s t o r s .…”

Section: Oxygen Diffusion Through the Grain Boundary Of Metal Oxidementioning

confidence: 99%

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

Tseng¹

2010

Solid State Circuits Technologies

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Introduction Motivation for implementing high dielectric constant gate dielectric for advanced CMOS scalingSemiconductor devices need to have good performance, with a low cost and low power dissipation. For decades, research and development of semiconductor processing technology and device integration have focused on enhancing performance and reducing costs using SiO 2 as the gate dielectric and doped polysilicon as the gate electrode. The most effective way to enhance performance and reduce costs is to scale the device gate length and gate oxide. Scaling the gate length results in fabricating more devices per wafer (i.e., increase the device density) and thus reduce the cost per chip, while scaling the gate oxide enhances the drive current and reduces the short channel effects due to gate length scaling. However, as the gate oxide becomes thinner, the power to operate transistors increases because of greater gate oxide leakage current. To resolve this high gate oxide leakage problem, the mechanism of the carriers tunneling through the gate dielectric must be better understood. In an ideal metal-insulator-semiconductor (MIS) device, the current conduction in the insulator should be zero. In a real MIS device, however, current can flow through the insulating film by various conduction mechanisms. The two primary conduction mechanisms for electron tunneling through high quality gate dielectric are discussed below. Direct tunnelingIn a metal-insulator-semiconductor (MIS) stack, when the oxide voltage (V ox ) is smaller than the metal-insulator barrier height, the electron tunnels directly from the metal electrode into other semiconductor electrode through the insulator. This is known as the direct tunneling process. The equation for direct tunneling current density (current normalized by device area) is proportional to

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Dopant penetration effects on polysilicon gate HfO/sub 2/ MOSFET's

Cited by 14 publications

References 1 publication

Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric

Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric

Hafnium-Based Gate Dielectric Materials

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

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