Double Dielectric Spacer for the Enhancement of Silicon p-Channel Tunnel Field Effect Transistor Performance

Abstract

A double dielectric spacer concept is proposed for the enhancement of the performance of silicon p-channel tunnel field effect transistor. The double dielectric spacer consist of an inner layer made of a high-k material and an outer layer made of a low-k material. We show that the double dielectric spacer with high-k inner layer result in the concentration of the external fringe field near the source to channel junction, resulting in the improvement of ON state currents without degrading the OFF state current or the subthreshold swing. Further we have illustrated improved dynamic performance of the double dielectric spacer architecture using mixed mode simulations of unloaded and capacitively loaded inverter circuits for the first time. Performance improvements are illustrated and explained for silicon dioxide, aluminium oxide and hafnium oxide gate dielectrics.

Fabrication of p-Type Double Gate and Single Gate Junctionless Silicon Nanowire Transistor by Atomic Force Microscopy Nanolithography

“…Scaling down the size of the transistors and the gate length of metal-oxide-semiconductor field-effect transistors (MOSFETs) raised several issues such as short channel effect (SCE), leakage current or low current. Several methods suggested to conquer these problems, such as high κ dielectrics [1], metal gate electrodes [2], and new transistor architectures based on silicon-on-insulator (SOI), such as FinFETs [3] or gate-all-around FETs [4]. Junction less transistors (JLTs) appeared to be the new and promising alternative for the new generation of transistors [5][6].…”