Double Differential Blocks Based Frequency Compensation: A Four-Stage CMOS Amplifier

Sanaei, Ali Mohammad; Biabanifard, Ali; Khadem, Mohammad Saeed; Aghaee, Toktam

doi:10.1142/s0218126622502735

Cited by 8 publications

(4 citation statements)

References 23 publications

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“…The main drawback of NMC and RNMC is needing large-value Miller capacitors. 15,16 For instance, almost a larger than 100 pF compensation capacitor is required for a 100 pF load capacitor. This limitation may satisfy designers to consider compensation capacitors off-chip.…”

Section: Introductionmentioning

confidence: 99%

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Four stage CMOS operational amplifier, frequency compensated via active miller network

Attar,

Dehbovid,

Ghorbani

et al. 2023

Engineering Reports

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A four‐stage CMOS operational amplifier is proposed in this work. The designed amplifier is frequency compensated via two differential blocks and two Miller capacitors. Unlike well‐known frequency compensation methods, the proposed compensation leaves the output node while exploiting extremely smaller capacitors compared to conventional approaches. The presented approach is modeled symbolically and realized at the circuit level via the Hspice circuit simulator and 0.18 μm CMOS technology. Good agreements between two separate simulation paths verify the validity and accuracy of the proposed approach. Ample simulation results are reported to investigate the proposed amplifier regarding parameter mismatches. According to the simulation results, the proposed four‐stage amplifier is an excellent candidate to be used in larger systems such as data converters, modulators, and sensors while it shows more than 169 dB as DC‐gain, 10 MHz as unity gain frequency with power consumption less than 500 μW.

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Section: Introductionmentioning

confidence: 99%

“…These two methods, perform frequency compensation via two Miller loops. The main drawback of NMC and RNMC is needing large‐value Miller capacitors 15,16 . For instance, almost a larger than 100 pF compensation capacitor is required for a 100 pF load capacitor.…”

Section: Introductionmentioning

confidence: 99%

Four stage CMOS operational amplifier, frequency compensated via active miller network

Attar,

Dehbovid,

Ghorbani

et al. 2023

Engineering Reports

View full text Add to dashboard Cite

show abstract

“…In this regard any DC gain is obtainable easily while challenge tend to instability effects 6–8 . In this vein, a traditional view is adding some passive and/or active elements as compensation network 9–17 . So numerous methods and approaches are reported to frequency compensating multi‐stage amplifiers.…”

Section: Introductionmentioning

confidence: 99%

“…[6][7][8] In this vein, a traditional view is adding some passive and/or active elements as compensation network. [9][10][11][12][13][14][15][16][17] So numerous methods and approaches are reported to frequency compensating multi-stage amplifiers. Among most famous methods, nested miller compensation (NMC) and reverse nested miller compensation (RNMC) are presented for three stage cases and also developed further with extra nulling resistors, voltage and current buffers.…”

Section: Introductionmentioning

confidence: 99%

Five‐stage CMOS OTAfrequency compensated via nested differential feedback

Zanjani

Sadrnia

Biabanifard

2022

Int J Numerical Modelling

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Nowadays cascode structures or vertical arrangements of MOSFETs can not satisfy demands regarding high gain amplifiers. As a direct result, the only promising choice turns to Multi-stage amplifiers via cascading gain stages. The challenge here is stability issues which shows itself by different frequency compensation. All problem starts with increasing number of nodes and consequent poles. The poles degenerate phase of system and need to be controlled. In this work, a five-stage amplifier is targeted for a new and efficient frequency compensation technique. The major contribution of proposed approach is using only two Miller capacitors with considerable small values (10 pF) compared to load capacitor (500 pF). This achieved via exploiting two differential active stages which intensify Miller effect and provide capability to share Miller capacitor at multiple loops simultaneously. The proposed amplifier with corresponding frequency compensation is described symbolically while a circuit level implementation is performed via HSPICE circuit simulator and TSMC 0.18 μm CMOS technology. Based on simulation results, the proposed amplifier expresses a DC gain of 195 dB, a gain bandwidth product of 15.2 MHz, a phase margin of 90 , and a power dissipation of 570 μW.

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