Double dual slope multiplier‐cum‐divider

Abstract

A novel type of analogue multiplier-cum-divider is described. A square waveform of period T which is proportional to V 2 /V 1 , where V 2 and V 1 are the two input applied voltages, is generated. Another input voltage V 3 is integrated during the period T. The peak value of the integrated output is V 2 V 3 /V 1 .Introduction: There are several multiplier circuits: (i) the sigma-delta or time division multiplier, (ii) the pulse width integrated multiplier, (iii) the double single slope multiplier and (iv) the pulse position sampled multiplier.If the width of a pulse train is made proportional to one voltage and the amplitude of the pulses to a second voltage, then the average value of the pulse waveform is proportional to the product of the two voltages, and is called the time division multiplier or the sigma-delta multiplier [1]. A pulse train of ON time proportional to one voltage is generated. Another voltage is integrated during the ON time of the pulse. The peak value of the integrated output is proportional to the product of the two voltages. This is called the pulse width integrated multiplier [2]. A short pulse train whose period T is proportional to one input voltage is generated. Another input voltage is integrated during the period T. The peak value of the integrated output is proportional to the product of the two input voltages. This is called the dual single slope multiplier [3]. A sawtooth wave of period T whose peak value is proportional to the one input voltage is sampled by a sampling pulse whose position over the period T is proportional to another input voltage. The sampled output is proportional to the product of two input voltages. This is called the pulse position sampled multiplier [4]. A square/triangular waveform is generated whose time period T is proportional to the one input voltage (V 1 ). Another input voltage (V 2 ) is integrated during the time period T. The peak value of the integrated output is proportional to the multiplication of V 2 V 1 . This is called a double dual slope analogue multiplier and is explained in this Letter.There are several ways for analogue division: (i) an antilogue network configuration; (ii) dividers using a field effect transistor (FET) [5]; the fact that an FET can be used as a voltage-dependent resistor, albeit within restricted gate-to-source voltage limits, is exploited in this method; (iii) a different method converts the input voltages to equivalent frequencies; takes the ratio of two frequencies by using conventional digital techniques, and then produces an output voltage proportional to the period of this ratio-metric signal [6]; (iv) dividers consist of four MOSFETs biased in weak inversion [7]; (v) employing a multiplier in a feedback loop of an opamp [8].A square waveform is generated whose time period T is inversely proportional to the one input voltage (V 1 ). Another input voltage (V 2 ) is integrated during the time period T. The peak value of the integrated output is proportional to the division V 2 /V 1 . This is called a double dual slo...