Double-Gate Negative-Capacitance MOSFET With PZT Gate-Stack on Ultra Thin Body SOI: An Experimentally Calibrated Simulation Study of Device Performance

Abstract

In this work, we propose and investigate the high performance and low power design space of non-hysteretic negative capacitance MOSFETs for the 14 nm node based on the calibrated simulations using an experimental gate stack with PZT ferroelectric to obtain negative capacitance effect. All necessary parameters are extracted by carefully characterizing experimentally fabricated ferroelectric capacitors, to ensure realistic simulation results. The ferroelectric thickness obtained by the proposed approach leads to the maximum enhancement in the non-hysteretic operation of negative capacitance transistors. We report a clear and significant double improvement in (i) subthreshold swing and (ii) gate overdrive, using negative capacitance effect. Simulations using Silvaco TCAD coupled with a realistic Landau model of ferroelectrics demonstrates that a 14 nm node UTBB FDSOI-FET can operate at 0.26 V instead of 0.9 V gate voltage using negative capacitance effect, with an average subthreshold swing of 55 mV/decade at room temperature. The double gate structure is proposed to overcome the large mismatch between the ferroelectric and MOS capacitor to enhance the negative capacitance effect and reduce the ferroelectric's optimized thickness. A 14 nm node DG-NCFET can operate at 0.24 V gate voltage with an average subthreshold swing of 45 mV/decade.

Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study

“…A negative capacitor in the gate stack can make the total capacitance larger than its classical value, which leads to the decrease of the required ∆V g to provide the same ∆ψ s . The challenges of ferroelectrics NC integration with conventional transistors are related to achieving simultaneously a matched design of the ferroelectric and in-series stabilizing MOS capacitors [5], [6]. In this context, a significant boosting can occur while the device behavior is still Ali non-hysteretic [6].…”

“…The challenges of ferroelectrics NC integration with conventional transistors are related to achieving simultaneously a matched design of the ferroelectric and in-series stabilizing MOS capacitors [5], [6]. In this context, a significant boosting can occur while the device behavior is still Ali non-hysteretic [6]. This paper experimentally investigates the impact of the NC on DC electrical characteristics of Tunnel FETs (TFETs) and MOSFETs.…”

“…In order to have a sufficient boosting of performance due to the NC effect, the absolute value of the ferroelectric negative capacitance (|C F E |) and the intrinsic gate capacitance (C int ) need to be relatively close [5], [9]. In order to achieve a negative capacitance transistor in the non-hysteretic operation mode, the series combination of the ferroelectric negative capacitance and C int should remain positive in the whole range of the operation [6]. A negative value of the total capacitance leads to instability and hysteretic jumps in the polarization that results in a hysteretic transfer characteristic.…”

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance

“…The challenges of using BTBT together with the NC in a single device are related to the matched design of the capacitances (ferroelectric and in-series stabilizing MOS capacitance) in a regime of operation, where a significant boosting of TFET electrical performance can be achieved [5,17,14]. In order to have a non-hysteretic NC switch, the total capacitance of the gate needs to be positive in the whole range of the operation [16]. Accordingly, the matching condition of the NC-TFET to have a sufficient amplification in the nonhysteretic operation of the device can express as it follows [14,18,5,17,19]:…”

Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation

“…The underlying idea consists of exploiting the negative capacitance region of ferroelectric materials, defined as C F E = dQ/dV F E , where Q and V F E refer to the charge density and the voltage drop over the ferroelectric, respectively [9], [10]. A ferroelectric capacitor (FE) in series with a dielectric capacitor (DE) of a proper value can be biased in the negative capacitance region, providing a larger capacitance than the constituent DE capacitor [11]. In order to have a non-hysteretic NCFET, the ferroelectric NC and DE capacitor should be well matched to provide a positive total capacitance in the whole range of the operation [12], [13] while the slope of the charge line is smaller than the negative slope of the FE polarization [14], [15].…”