Double node charge sharing SEU tolerant latch design

Katsarou, Katerina; Tsiatouhas, Yiorgos

doi:10.1109/iolts.2014.6873683

Cited by 39 publications

(38 citation statements)

References 21 publications

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“…However, the DICE latch has a partial DNCS-SEU tolerance [3], [20]. An enhanced alternative topology is TPDICE [21] where the four-stage DICE cell is extended to six stages.…”

Section: Seu Tolerant Latch Designsmentioning

confidence: 99%

“…Alternative SEU protection latch designs such as the BISER topology [7] and the FERST scheme [22] do not provide DNCS-SEU protection [20].…”

Section: Seu Tolerant Latch Designsmentioning

confidence: 99%

“…Finally, a latch topology was proposed in [20] that ensures complete DNCS-SEUs tolerance. However, the efficiency of this topology has a cost in terms of propagation delay, power consumption and silicon area.…”

Section: Seu Tolerant Latch Designsmentioning

confidence: 99%

“…However, the efficiency of this topology has a cost in terms of propagation delay, power consumption and silicon area. A new latch design is proposed in this work that provides complete immunity to DNCS-SEUs, at a lower signal propagation delay dynamic power consumption and silicon area cost with respect to [20].…”

Section: Seu Tolerant Latch Designsmentioning

confidence: 99%

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Soft error immune latch under SEU related double-node charge collection

Katsarou

Tsiatouhas

2015

2015 IEEE 21st International on-Line Testing Symposium (IOLTS)

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“…However, the DICE latch has a partial DNCS-SEU tolerance [3], [20]. An enhanced alternative topology is TPDICE [21] where the four-stage DICE cell is extended to six stages.…”

Section: Seu Tolerant Latch Designsmentioning

confidence: 99%

“…Alternative SEU protection latch designs such as the BISER topology [7] and the FERST scheme [22] do not provide DNCS-SEU protection [20].…”

Section: Seu Tolerant Latch Designsmentioning

confidence: 99%

Section: Seu Tolerant Latch Designsmentioning

confidence: 99%

Section: Seu Tolerant Latch Designsmentioning

confidence: 99%

See 2 more Smart Citations

Soft error immune latch under SEU related double-node charge collection

Katsarou

Tsiatouhas

2015

2015 IEEE 21st International on-Line Testing Symposium (IOLTS)

Self Cite

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“…Several layout techniques, such as soft error immune latch (SEILA) [10], layout design through error aware transistor positioning (LEAP) [11], have been proposed to attenuate the charge collection on multi-node. And at circuit-level, Katsarou et al proposed the DNCS-SEU tolerant latch to deal with the charge sharing [12]. Although this technology can efficiently attenuate the multi-node charge collection, the area and power overhead is too large.…”

Section: Introductionmentioning

confidence: 99%

Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches

Zeng

2015

IEICE Electron. Express

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In this paper, we propose a novel hardened latch to mitigate the SEU. The combination of the circuit structure and layout placement is adopted to enhance the multiple nodes upset tolerance. This latch consists of a normal D latch and a typical DICE latch. Different from the TMR latch, this latch can mitigate the charge collection on two transistors. HSPICE simulation results present that there only exit four sensitive transistor pairs in this latch. Compared to the typical DICE and DMR latch, the sensitive transistor pairs are largely reduced. And by adjusting the layout placement, these sensitive transistor pairs are separated from each other as much as possible. From the view of the layout, it is almost impossible for charge collection on the sensitive transistor pairs in our proposed latch.

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An ultra low‐power double‐node‐upsets hardened latch design

Chen,

Xie,

Liang

et al. 2024

Circuit Theory & Apps

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In this paper, a novel low‐cost, double‐node upset (DNU) tolerant latch aiming at nourishing the lack of these devices in the state of the art was presented, especially featuring high reliability while maintaining a low‐cost profile. The proposed latch is based on a low‐cost single event double‐node upset tolerant latch and also provides self‐recoverability against double‐node‐upsets. The latch uses clock‐controlled DICE (Dual‐interlocked storage cell) cell and CE(C‐Elements) cell to tolerate double‐node‐upsets fully. The Simulation waveforms and analysis results show that the proposed latch can maintain the correct output in any case of DNU. In addition, under the premise of high radiation tolerance, the minimum improvement of the area‐power‐delay product (APDP) of the proposed low‐power double‐node‐upsets hardened latch (LPDHL) is 16.60%, compared with the latest DNU tolerant latch on the literature.

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Double node charge sharing SEU tolerant latch design

Cited by 39 publications

References 21 publications

Soft error immune latch under SEU related double-node charge collection

Soft error immune latch under SEU related double-node charge collection

Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches

An ultra low‐power double‐node‐upsets hardened latch design

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