Double patterning lithography friendly detailed routing with redundant via consideration

Yuan, Kun; Lu, Katrina; Pan, David Z.

doi:10.1145/1629911.1629930

Cited by 25 publications

(8 citation statements)

References 6 publications

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“…A lot of work focused on developing multiple patterningaware routers, like LELE-aware routing, [20][21][22] triple patterning-aware routing, 23 SADP-, and SAQP-aware routing. 24,25 However, none of these works offered a pattern-centric design rule evaluation method, and this is the main contribution of our work.…”

Section: Prior Workmentioning

confidence: 99%

Layout pattern-driven design rule evaluation

Badr

Gupta

2014

SPIE Proceedings

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Abstract. With the use of subwavelength photolithography, some layouts can have low printability and, accordingly, low yield due to the existence of bad patterns even though they pass design rule checks. A reasonable approach is to select some of the candidate bad patterns as forbidden. These are the ones with a high yield impact or low routability impact, and these are to be prohibited in the design phase. The rest of the candidate bad patterns may be fixed in the postroute stage in a best-effort manner. The process developers need to optimize the process to be friendly to the patterns of high routability impact. Hence, an evaluation method is required early in the process to assess the impact of forbidding layout patterns on routability. We propose pattern-driven design rule evaluation (pattern-DRE), which can be used to evaluate the importance of patterns for the routability of the standard cells and, accordingly, select the set of bad patterns to forbid in the design. The framework can also be used to compare restrictive patterning technologies [e.g., litho-etch-litho-etch (LELE), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), self-aligned octuple patterning (SAOP)]. Given a set of design rules and a set of forbidden patterns, pattern-DRE generates a set of virtual standard cells; then it finds the possible routing options for each cell without using any of the forbidden patterns. Finally, it reports the routability metrics. We present a few studies that illustrate the use cases of the framework. The first study compares LELE to SADP by using a set of forbidden patterns that are allowed by LELE but not by SADP. Another study compares LELE to extreme ultraviolet lithography from the routability aspect by prohibiting patterns that have LELE native conflicts. In addition, we present a study that investigates the effect of placing the active area of the transistors close to the P/N interface instead of close to the power rails.

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Section: Prior Workmentioning

confidence: 99%

Layout pattern-driven design rule evaluation

Badr

Gupta

2014

SPIE Proceedings

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“…Therefore, Cho et al [14] proposed the first DPT -aware detailed routing algorithm which simultaneously finds a DPT -friendly routing path and corresponding layout decomposition for each net; as a result, they perform LD in the routing stage and apply rerouting to reduce conflict. Afterward, Yuan et al [40] proposed DPT friendly detailed routing, which considers not only LD but also redundant vias in the detailed routing.…”

Section: Double-patterning Technologymentioning

confidence: 99%

Recent research development in physical design for manufacturability

Chen

Lai

et al. 2011

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

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As IC process geometries scale down to the nanometer era, the industry faces severe challenges of manufacturing limitations. For the imperfect manufacturing process, physical design for manufacturability has played an essential role in resolution and thus yield enhancement to guarantee yield. In this paper, we introduce three major challenges arising from the nanometer process technology and survey major existing techniques for handling the challenges in physical design for manufacturability.

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“…The first detailed routing algorithms that have been proposed for multiple patterning technologies [3], [4], [5], [6] have been targeted at the LELE ("litho-etch-litho-etch") double patterning technology, where objects on each layer are assigned to two different masks that are also referred to as colors. These approaches have in common that they assume the availability of stitching and jogs, which is not always realistic.…”

Section: Introductionmentioning

confidence: 99%

Detailed Routing Algorithms for Advanced Technology Nodes

Ahrens

Gester

Klewinghaus

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In our paper we present new detailed routing algorithms dealing with challenges in advanced technology nodes, such as complex design rules and multiple patterning. We combine our routing tool, BonnRoute, with an industrial router for cleaning up remaining design rule violations and demonstrate superior routing results over that industrial router on real-world multiple patterning designs. This paper has never been submitted for publication anywhere else.On behalf of all authors, Michael GesterAbstract-We present algorithms for routing in advanced technology nodes, used by BonnRoute to obtain efficient and almost design rule clean wire packings and pin access solutions. Designs with dense standard cell libraries in presence of complex industrial design rules, with a special focus on multiple patterning lithography, are considered. The key components of this approach are a multi-label interval-based shortest path algorithm for long on-track connections, and a dynamic program for computing packings of pin access paths and short connections between closely spaced pins. The multi-label path search implementation is very general and is driven with different labeling rules, allowing to trade off runtime against accuracy in terms of obeyed design rules. We combine BonnRoute with an industrial router for cleaning up the remaining design rule violations, and demonstrate superior results over that industrial router in our experiments in terms of wire length, number of vias, design rule violations and runtime.

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Double patterning lithography friendly detailed routing with redundant via consideration

Cited by 25 publications

References 6 publications

Layout pattern-driven design rule evaluation

Layout pattern-driven design rule evaluation

Recent research development in physical design for manufacturability

Detailed Routing Algorithms for Advanced Technology Nodes

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