Double-pulse-single-event transients in combinational logic

This paper intends to present a novel radiation-hardened SRAM cell by using the PMOS transistors stacked (each PMOS is split into two same sizes) and changing the inner topological structure on basis of the Quatro-10T. Combined with layout-level optimization design, the 3-D TCAD mixed-mode simulation results show that the novel design has a great single event upset (SEU) immune. Simultaneously, it is found to be tolerant of partial single-event multiple-node upsets (SEMNUs) due to the charge sharing among off-PMOS transistors. In addition, compared with the Quatro-10T, our proposed structure exhibits larger static noise margin (SNM) as well as lower power consumption in 65 nm COMS technology.

Section: Simulation Results and Analysismentioning

confidence: 99%

A radiation harden enhanced Quatro (RHEQ) SRAM cell

Peng

Chen

Zhang

et al. 2017

“…Three-dimensional mixed-mode (TCAD) simulation is adopted in this paper, which has been proven to be a useful means of investigating single-event effects (SEEs) in ICs [20,27,28,29,30]. The MOSFETs used in storage structures of these latches are built with the use of TCAD numerical models, and the others employ the SPICE models.…”

Section: Seu Tolerancementioning

confidence: 99%

“…The angle striking of heavy ion has been investigated in the current paper as well. Angle 60°is widely adopted in simulations to perform the influence of the ion striking angle on device [27,28,29,30]. Thus, we set the angle between the +y-axis and the direction of the ion striking to 60°.…”

Section: Seu Tolerancementioning

confidence: 99%

A single event upset tolerant latch with parallel nodes

Liu

Lin

et al. 2019

A single event upset (SEU) tolerant latch has been put forward in the current paper. By means of the parallel nodes structure design together with the layout-level optimization design, the proposed design is capable of substantially improving the immunity to SEU. In comparison with the conventional latch, the stacked latch with isolation and the dualmodular-redundancy (DMR) latch with C-element, the simulation results based on the 65 nm CMOS process demonstrate that the proposed latch performs much better in SEU mitigation. For P-hit simulation, the proposed latch can achieve a correct output in the end, no matter the struck PMOS is at OFF state or ON state. For N-hit simulation, the proposed latch is also capable of mitigating the voltage transient and recovering to original state eventually.

“…We also study the impact of the ion strike angles on the circuits. Angle 60°is widely used in simulations to evaluate the dependence of ion striking angle on SET [13,14,15]. So, in the angle striking simulations, the angle between the direction of ion striking and the +y-axis is set to 60°.…”

Section: P-hit 1)mentioning

confidence: 99%

An inverter chain with parallel output nodes for eliminating single-event transient pulse

Chang-yong

Lin

et al. 2019

The current paper presents an inverter chain with parallel output nodes design for the purpose of eliminating the single-event transient (SET) pulse. The structure of parallel output nodes combined with the layout utilizing isolation approach can eliminate the SET pulse substantially. As compared with the conventional inverter chain as well as the inverter chain of source-isolation approach and the duplicated inverter chains with C-element, the simulation results illustrate that the proposed inverter chain manifests an effective improvement of immunity to SET. With regard to P-hit, the proposed inverter chain is capable of attaining a stable output irrespective of the state of the struck PMOS being OFF or ON. With regard to N-hit, the proposed inverter chain can also maintain the final output steadily. As long as the SET pulse is not generated at the eventual output node, the pulse can be eliminated by the proposed inverter chain. Besides that, the proposed approach is also applicable to the circuits with the structure like inverter chain.