DPCS

Abstract

Fault-Tolerant Voltage-Scalable (FTVS) SRAM cache architectures are a promising approach to improve energy efficiency of memories in the presence of nanoscale process variation. Complex FTVS schemes are commonly proposed to achieve very low minimum supply voltages, but these can suffer from high overheads and thus do not always offer the best power/capacity trade-offs. We observe on our 45nm test chips that the "fault inclusion property" can enable lightweight fault maps that support multiple runtime supply voltages. Based on this observation, we propose a simple and low-overhead FTVS cache architecture for power/capacity scaling. Our mechanism combines multilevel voltage scaling with optional architectural support for power gating of blocks as they become faulty at low voltages. A static (SPCS) policy sets the runtime cache VDD once such that a only a few cache blocks may be faulty in order to minimize the impact on performance. We describe a Static Power/Capacity Scaling (SPCS) policy and two alternate Dynamic Power/Capacity Scaling (DPCS) policies that opportunistically reduce the cache voltage even further for more energy savings. This architecture achieves lower static power for all effective cache capacities than a recent more complex FTVS scheme. This is due to significantly lower overheads, despite the inability of our approach to match the min-VDD of the competing work at a fixed target yield. Over a set of SPEC CPU2006 benchmarks on two system configurations, the average total cache (system) energy saved by SPCS is 62% (22%), while the two DPCS policies achieve roughly similar energy reduction, around 79% (26%). On average, the DPCS approaches incur 2.24% performance and 6% area penalties.

A fault-tolerant last level cache for CMPs operating at ultra-low voltage

“…The energy results shown above do not consider any block power gating technique [38]. Assuming a more aggressive approach, where fine-grained block power gating is affordable [39], the benefits of BD-based techniques in terms of power and energy will be enhanced, as faulty entries do not consume static power during operation. Applying this technique, the EPI with BDOT-NRR-FA would be 6.2%, 6.7%, 7.2%, 6.3%, and 5.5% lower for the multiprogrammed workloads than the EPI values in Figure 10 with C6, C5, C4, C3, and C2 cells, respectively.…”

A dual V t disturb-free subthreshold SRAM with write-assist and read isolation

“…Leakage power consumption and short-channel effects increase exponentially with the device scaling and ever increasing chip area enjoyed by SRAM, which continues to be a major cause of power dissipation [2] . Since SRAM stays mostly idle, leakage power is the major power consumer [3] . Numerous solutions have been sought including silicon on insulator, hetero-devices, FinFETs [4][5][6] , strained silicon and micro electro-mechanical systems [7] to solve this problem.…”

Software and hardware interfaces for approximate memories

“…Memory cells are intrinsically sensitive to circuit variability due to the size of components and dense layouts [42]. External factors, such as process variation and temperature, may affect the data and cause errors, thus vendors define the nominal values of memory parameters according to the worst-case operating conditions to guard-band a secure margin to ensure reliability [13,94].…”

“…Reliability concerns are the focus of modern memory devices [42]. Volatile and nonvolatile memories face problems in aspects of scaling, performance, energy, or aging that may affect the reliability of the stored data [12,64,84].…”