DPN Treatment plus Annealing Temperatures for 28nm HK/MG nMOSFETs with CHC Stress

Abstract

The possible nano-crystallization formation and thicker interface layer at the higher annealing atmosphere, however, is easy to suppress the superiority of high-k dielectric deposition in the improvement of drive current and reliability. This phenomenon was apparently observed at 900 o C annealing tested devices after the nitridation process. The drive current at 900 o C annealing before hot-carrier stress is lower than that at 700 o C with the same nitrogen concentration and the same feature sizes. After the hot-carrier stress test at 125 o C ambience, the degradation of the threshold voltage shift at 900 o C is still the worst among all of tested samples. DPN 700 o C DPN 900 o C DPN 700 o C DPN 900 o C DPN 700 o C DPN 900 o C