Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction

Chen, Gengjie; Jiang, Bentian; Chen, Jingsong; Young, Evangeline F. Y.

doi:10.1109/iccad45719.2019.8942074

Cited by 42 publications

(8 citation statements)

References 16 publications

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“…Secondly, the superiority of our proposed DAMO is also validated by thorough experiments. Lastly, we test our model using the fullchip layout in ISPD 2019 contest [30], which is generated by an open-source router [31].…”

Section: Resultsmentioning

confidence: 99%

Damo

Chen

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: Resultsmentioning

confidence: 99%

Damo

Chen

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…Xu et al [23] address the pin accessibility problem under self-aligned double patterning constraints. More recently, Sun et al [19], Kahng et al [10], Bai et al [2] and Li et al [11] present alternative solutions to address pin accessibility during initial detailed routing in advanced technology nodes. Chan et al [5] proposes a machine learning alternative that helps routability for Sub-14nm Process Node technologies, which includes techniques that deal with pin density and proximity.…”

Section: B Related Workmentioning

confidence: 99%

Algorithms for Access Point Selection at Pre-Routing Stage

Danigno

Fogaça

Monteiro

et al. 2021

JICS

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Pin accessibility has arisen as a major issue for detailed routing due to the increased number of design rules and higher pin density of modern technology nodes. The existing literature tackles this problem across many stages of the design flow: standard-cell layout, placement optimization and routing. In our present work, we cope with the pin accessibility challenge as a pre-processing step for detailed routing. We devise five techniques to find on-track locations in which the router can access I/O pins of standard cell instances without causing design rule violations (DRVs.) We provide the algorithm complexity analyses for each of our techniques. Some of our methods tackle the complexity of checking the design rules using pessimism (i.e., they are subject to false positives). We also study the cases in which our methods are overly pessimistic and ways to overcome pessimism. Finally, we validate our techniques using the 45 and 32 nanometer designs from the ISPD 2018 contest on initial detailed routing and show that our most robust technique can find DRV-free access points for more than 99\% of the pins of the test cases in less than 5 minutes.

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“…Routing tracks with preferred direction are standard in digital detailed routing. The state-of-the-art digital detailed routers [9,10] perform routing on such structure and minimize the wrong-way and off-track wires. Analog circuit designers typically adopt the shape-based gridless routing methodology for connections, especially in bulk CMOS designs.…”

Section: Routing Grid Graphmentioning

confidence: 99%

“…For those pins not covering a same-layer grid point, we adopted the concept in [10] to find an access point in other layers, without setting the preferred access direction. However, in practical analog designs, most of the pins have at least one same-layer access point since the scale of an analog device is typically more substantial.…”

Section: Pin Access Assignmentmentioning

confidence: 99%

“…The detailed routing problem has been broadly studied for decades. Recent efforts show promising progress to diminish the gap between academic and real-world physical design needs [9,10,20]. Despite the revival of detailed routing research in recent years, limited work has demonstrated an end-to-end detailed routing scheme for analog/mixed-signal (AMS) circuits.…”

Section: Introductionmentioning

confidence: 99%

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