DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators

Bostanci, F. Nisa; Olgun, Ataberk; Orosa, Lois; Yağlıkçı, A. Giray; Kim, Jeremie S.; Hassan, Hasan; Ergin, Oğuz; Mutlu, Onur

doi:10.1109/hpca53966.2022.00087

Cited by 13 publications

(3 citation statements)

References 134 publications

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“…⃝ that suits the particular DRAM chip under test. Prior works extensively study key aspects of effective test methodologies, including appropriate data and access patterns, the effects of enabling/disabling DRAM chip features such as target row refresh (TRR) [23,28,32,48,301] and on-die error correcting codes (on-die ECC) [38-40, 87, 115, 143, 166, 168, 230, 361-363], and the viability of different DRAM command sequences (e.g., sequences that enable in-DRAM row copy operations [55,90,96,364], true randomnumber generation [75,91,266,365], and physically unclonable functions [73,267]).…”

Section: Information Flow During Testingmentioning

confidence: 99%

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today's DRAM technology scaling challenges requires new solutions driven by both DRAM producers and consumers. In this paper, we observe that the separation of concerns between producers and consumers specified by industry-wide DRAM standards is becoming a liability to progress in addressing scaling-related concerns.To understand the problem, we study four key directions for overcoming DRAM scaling challenges using system-memory cooperation: (i) improving memory access latencies; (ii) reducing DRAM refresh overheads; (iii) securely defending against the RowHammer vulnerability; and (iv) addressing worsening memory errors. We find that the single most important barrier to advancement in all four cases is the consumer's lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, we recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, we propose adopting this revision in a two-step plan, starting with immediate information release through crowdsourcing and publication and culminating in widespread modifications to DRAM standards.

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Section: Information Flow During Testingmentioning

confidence: 99%

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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“…Since Hyper-A and IMP target in-emerging-NVM substrates that utilize different computing paradigms (e.g., associative processing [186,187]) or rely on particular structures of the NVM array (such as analog-to-digital/digital-to-analog converters) to perform computation, they are not applicable to an in-DRAM substrate that performs bulk bitwise operations. Olgun et al propose the PiDRAM [188] framework, a flexible end-to-end and open-source FPGA-based framework that enables system integration studies and evaluation of in-DRAM computing techniques (e.g., in-DRAM copy and initialization [86,98] and in-DRAM true random generation [108,189,190]) using real unmodified DRAM chips. PiDRAM is publicly available at [191] and can be used to prototype our SIMDRAM framework in a real system.…”

Section: Discussionmentioning

confidence: 99%

Methodologies, Workloads, and Tools for Processing-in-Memory: Enabling the Adoption of Data-Centric Architectures

F.¹,

Gómez-Luna²,

Ghose³

et al. 2022

Preprint

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“…To conduct accurate and rigorous testing, the system designer must use an e ective test methodology 2 that suits the particular DRAM chip under test. Prior works extensively study key aspects of e ective test methodologies, including appropriate data and access pa erns, the e ects of enabling/disabling DRAM chip features such as target row refresh (TRR) [100,160,216,222,239] and on-die error correcting codes (on-die ECC) [23,26,28,30,54,95,[254][255][256][257][258][259], and the viability of di erent DRAM command sequences (e.g., sequences that enable in-DRAM row copy operations [138,139,142,260], true random-number generation [140,141,261,262], and physically unclonable functions [97,263]).…”

Section: Information Flow During Testingmentioning

confidence: 99%

A Case for Transparent Reliability in DRAM Systems

Patel¹,

Shahroodi²,

Manglik³

et al. 2022

Preprint

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Mass-produced commodity DRAM is the preferred choice of main memory for a broad range of computing systems due to its favorable cost-per-bit. However, today's systems have diverse system-speci c needs (e.g., performance, energy, reliability) that are di cult to address using one-size-ts-all generalpurpose DRAM. Unfortunately, although system designers can theoretically adapt commodity DRAM chips to meet their particular design goals (e.g., by exploiting slack in access timings to improve performance, or implementing system-level RowHammer mitigations), we observe that designers today lack the necessary insight into commodity DRAM chips' reliability characteristics to implement these techniques in practice. In this work, we make a case for DRAM manufacturers to provide increased transparency into simple device characteristics (e.g., internal row address mapping, cell array organization) that a ect consumer-visible reliability. Doing so has negligible impact on manufacturers given that these characteristics can be reverse-engineered using known techniques; however, it has signi cant bene t for system designers, who can then make informed decisions to be er adapt commodity DRAM to meet modern systems' needs while preserving its cost advantages.To support our argument, we study four ways that system designers can adapt commodity DRAM chips to system-speci c design goals: (1) improving DRAM reliability; (2) reducing DRAM refresh overheads; (3) reducing DRAM access latency; and (4) defending against RowHammer a acks. We observe that adopting solutions for any of the four goals requires system designers to make assumptions about a DRAM chip's reliability characteristics. ese assumptions discourage system designers from using such solutions in practice due to the di culty of both making and relying upon the assumption.We identify DRAM standards as the root of the problem: current standards rigidly enforce a xed operating point with no speci cations for how a system designer might explore alternative operating points. To overcome this problem, we introduce a two-step approach that reevaluates DRAM standards with a focus on transparency of reliability characteristics so that system designers are encouraged to make the most of commodity DRAM technology for both current and future DRAM chips.

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DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators

Cited by 13 publications

References 134 publications

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Methodologies, Workloads, and Tools for Processing-in-Memory: Enabling the Adoption of Data-Centric Architectures

A Case for Transparent Reliability in DRAM Systems

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