Drain bias and position dependent performance degradation of dual-gate poly-Si TFTs with undoped region offsets

Hsu, Chih-Chieh; Chen, Po-Tsung

doi:10.1088/1361-6641/ab1a8f

Cited by 3 publications

(3 citation statements)

References 39 publications

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“…The I DS -V GS curves are highly in agreement with the measurement data of the TFT. The comparison has been reported in our previous study [32]. Based on this TFT TCAD model, we further simulated the transfer characteristics of the TFTs with t poly of 140 nm (TFT-A) and 20 nm (TFT-C).…”

Section: Transfer Characteristics Of the Dual-gate Tfts With Differen...mentioning

confidence: 83%

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Performance dependence of self-aligned dual-gate poly-Si TFTs on localized defective regions

Hsu¹,

Li²,

Chen³

et al. 2020

Semicond. Sci. Technol.

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This study investigates effects of localized defect regions on electrical characteristics of self-aligned dual-gate poly-Si thin-film transistors (TFTs). The thickness of the poly-Si channel layer ranges from 20 nm to 140 nm. The threshold voltage, subthreshold swing, and mobility are found to be sensitive to the defect position. The localized defects in the left channel (source side) exhibit a significant impact while those in the right channel (drain side) show a lower influence on the TFT performance. In addition, the performance variation caused by the localized defects in the right channel is highly sensitive to the magnitude of the applied drain bias. A higher drain bias can observably reduce the performance degradation. Effects of multiple defect regions on the electrical behavior of the TFTs are also explored. We found that the upper width of the defect regions dominates the TFT performance deterioration. The hole transport, hole concentration distributions, and current flowlines are analyzed to study the physical mechanisms.

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Section: Transfer Characteristics Of the Dual-gate Tfts With Differen...mentioning

confidence: 83%

“…Then, the TFT TCAD model was established based on the measurement data of the TFT. The details have been published in our previous study [32].…”

Section: Device Fabrication and Simulation Methodologymentioning

confidence: 99%

Performance dependence of self-aligned dual-gate poly-Si TFTs on localized defective regions

Hsu¹,

Li²,

Chen³

et al. 2020

Semicond. Sci. Technol.

Self Cite

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“…In order to reduce this high drain electric field, many structures have been proposed to overcome this problem. Offset [ 6 , 7 ], lightly doped drain (LDD) [ 8 ], gate overlapped lightly doped drain (GOLDD) [ 9 ], and raised source/drain (RSD) [ 10 , 11 , 12 ] are some of the proposed schemes that can effectively reduce the drain side electric field. Conventional RSD devices contain thick source/drain (S/D) regions and a thin channel, are not self-aligned in nature, and need additional masks [ 13 ].…”

Section: Introductionmentioning

confidence: 99%

Raised Source/Drain (RSD) and Vertical Lightly Doped Drain (LDD) Poly-Si Thin-Film Transistor

Chien

Yen

et al. 2021

Membranes

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The raised source/drain (RSD) structure is one of thin film transistor designs that is often used to improve device characteristics. Many studies have mentioned that the high impact ionization rate occurring at a drain side can be reduced, owing to a raised source/drain area that can disperse the drain electric field. In this study, we will discuss how the electric field at the drain side of an RSD device is reduced by a vertical lightly doped drain (LDD) scheme rather than a RSD structure. We used different raised source/drain forms to simulate the drain side electric field for each device, as well as their output characteristics, using Integrated Systems Engineering (ISE-TCAD) simulators. Different source and drain thicknesses and doping profiles were applied to verify the RSD mechanism. We found that the electric fields of a traditional device and uniform doping RSD structures are almost the same (~2.9 × 105 V/cm). The maximum drain electric field could be reduced to ~2 × 105 V/cm if a vertical lightly doped drain RSD scheme was adopted. A pure raised source/drain structure did not benefit the device characteristics if a vertical lightly doped drain design was not included in the raised source/drain areas.

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Study of Electrical Characteristics for Dual-Gate TFTs With Asymmetric Defect Distributions and Gate Work Functions

Hsu

Huang

et al. 2023

IEEE Trans. Electron Devices

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Drain bias and position dependent performance degradation of dual-gate poly-Si TFTs with undoped region offsets

Cited by 3 publications

References 39 publications

Performance dependence of self-aligned dual-gate poly-Si TFTs on localized defective regions

Performance dependence of self-aligned dual-gate poly-Si TFTs on localized defective regions

Raised Source/Drain (RSD) and Vertical Lightly Doped Drain (LDD) Poly-Si Thin-Film Transistor

Study of Electrical Characteristics for Dual-Gate TFTs With Asymmetric Defect Distributions and Gate Work Functions

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