Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective

Acharya, Abhishek; Solanki, Abhishek; Dasgupta, S.; Bulusu, Anand

doi:10.1109/ted.2017.2771249

Cited by 26 publications

(12 citation statements)

References 24 publications

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“…The authors also discuss that deep saturation is achieved when the source-to-drain separation gets depleted of carriers. However, as discussed in the previous sections, leakage tunneling, which is highly dependent on Vds, takes place in this region, overlapping the deep saturation mechanism discussed in [8]. This causes at least three consequences for the output conductance (gd): 1) it reaches a minimum value (around 1.5x10 -2 nS/µm and 3x10 -2 nS/µm for Lg=100 nm and 1µm, respectively) and rises in deep saturation; 2) for sufficiently high Vds and low Vgs, gd rises exponentially, completely degrading the transfer characteristics [5] once leakage tunneling gets similar in magnitude to line-tunneling and 3) the average value of gd does not depend upon the gate length because leakage tunneling does not take place under the gate.…”

Section: Output Conductance and Gate Lengthsupporting

confidence: 63%

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Output Conductance of Line-TFETs for Different Device Parameters and its Effect on Basic Analog Circuits

Filho

Martino²,

Agopian³

2020

JICS

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This work addresses the impact of different device parameters on the analog characteristics of Line-Tunneling Field Effect Transistors (Line-TFETs). Source-to-drain separation, pocket thickness, pocket doping, gate-source alignment and the gate length are varied in order to evaluate their impact on the conduction mechanisms and on the overall transfer characteristics of the device. The variation of the main parameters responsible for device variability (pocket thickness and doping and gate-source alignment) is performed in order to analyze their impact on current mirrors, revealing that gate-source overlap improves the analog characteristics of the Line-TFET and that pocket doping should be limited to values smaller than 1018cm-3. Even though the drain current and the transconductance (gm) of this device are proportional to the gate area, simulations compared to experimental data show that the output conductance (gd) of Line-TFETs is practically independent of the gate length. The conduction mechanisms were analyzed through numerical simulations, revealing that this unique characteristic is due to source-to-drain tunneling, which defines the average value of gd on the saturation-like region and does not depend upon the gate length. The impact of this characteristic on analog circuit design is illustrated considering the example of a common-source stage and comparing its design when using MOSFET devices. This example reveals that the designer may choose whether to increase gm or gd in order to increase the circuit gain when using Line-TFETs, fundamentally differing from the MOSFET design.

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Section: Output Conductance and Gate Lengthsupporting

confidence: 63%

“…In [8], the authors propose that soft saturation is achieved in this device when the source is depleted of carriers due to Vds increase. The authors also discuss that deep saturation is achieved when the source-to-drain separation gets depleted of carriers.…”

Section: Output Conductance and Gate Lengthmentioning

confidence: 99%

Output Conductance of Line-TFETs for Different Device Parameters and its Effect on Basic Analog Circuits

Filho

Martino²,

Agopian³

2020

JICS

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“…Further, observing the output characteristics for gated and non‐gated channels in Figure 13D, there is hardly any change in the drain saturation voltage and current. The only difference lies in the slope of the curve, which is slightly distorted in the presence of the additional ungated channel resistance, which is one issue with underlapped gate structures 43‐45 . However, this slope is highly dependent on source side conductance and its degeneracy and in turn on the source doping 43 .…”

Section: Resultsmentioning

confidence: 99%

Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET

Ashita

Loan

Alkhammash

et al. 2021

Int J Numerical Modelling

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In this work, we propose and investigate a new pocket‐based Si0.55Ge0.45/Si gate normal tunnel FET design employing a gate over source with a single lateral pocket (GSLP) with and without a heterogeneous dielectric (HD) gate oxide. Miller capacitance is significantly reduced with the GSLP design, which is further improved by the HD gate oxide leading to full overshoot/undershoot suppression capability in transient response. Further, a steep switching with more than one order improvement in ON current is achieved when compared to state‐of‐the‐art line pocket designs. As a result, an ~98.8% and ~88% improved intrinsic delay (CGGVDD/ION) is achieved in comparison to dual line pocket and non‐pocketed designs, respectively. Additionally, an improved worst‐case trap‐charge tolerance, reduced pocket‐width‐induced fluctuations, and excellent immunity to gate misalignment‐induced fluctuations are achievable just by replacing the gate‐aligned parallel‐line pockets with a vertically aligned single‐lateral pocket (LP) improving the design reliability. A Ge/Si HD‐GSLP TFET design further offers stable ON currents with SS < 60 mV/dec over a feasible range of pocket widths between ~6 and 8 nm at VDS = VGS = 0.7 V.

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“…The epitaxial layer and the intrinsic region both had a phosphorus doping concentration of 1 × 10 15 cm −3 , and both of them served as the channel of the devices. The thickness of ETL is tuned to 3 nm, as in [20]. To retain the abrupt doping profile of the source-channel and drain-channel, the thin ETL may be grown on silicon without producing serious defects using low-temperature plasma-deposition [22] or reduced pressure chemical vapor deposition [23].…”

Section: Device Structure and Simulationmentioning

confidence: 99%

“…However, Si tunnel FETs always suffer from a low ON-state current, I ON , that is well below the conduction current of CMOS devices [1], [8], [9]. Therefore, a variety of approaches have been proposed to boost the BTBT current, such as using lower band-gap materials at the source [9], [10] or fabricating TFETs with a high-κ gate dielectric [11]- [12], with doublegate [13], [14], with a high-κ spacer [15]- [17], and with a thin epitaxial tunnel layer (ETL) [17]- [20]. Although using a low bandgap material in the tunnel region works to increase the tunnel current, such devices subsequently have a high OFF-sate current, I OFF .…”

Section: Introductionmentioning

confidence: 99%

Gate Field Plate Structure for Subthreshold Swing Improvement of Si Line-Tunneling FETs

et al. 2019

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Tunnel field-effect transistors (TFETs) are promising for use in ultralow-power applications owing to their distinct band-to-band tunneling operation. However, the ON-state current of these Si-based tunnel devices is considerably lower than that of MOSFETs. Furthermore, a high-κ dielectric is used as a gate insulator or spacer to increase the TFET's tunneling field strength; this usually causes fringe-induced barrier lowering and deterioration of its subthreshold characteristics. Here, in this paper, a gate field plate TFET (GFP-TFET) structure is proposed to enhance the driving current and suppress the current kink induced by fringe-induced barrier lowering. A detailed investigation into the effects of a gate field plate on TFET performance was conducted with the help of extensive device simulations. The gate oxide and gate field plate oxide could be used to tailor the electric field lines to increase the electric field in the tunnel junction. Meanwhile, the fringing field concentration was reduced by using a metal with a relatively high work function as the field plate electrode. Thus, the electric field strength decreased near the gate edge and increased in the channel. The GFP-TFET exhibited high driving current and low subthreshold characteristics at the cost of a reduction in cutoff frequency. A GFP-TFET structure with optimized parameters had a 10 3 × higher ON-state current compared with a normal silicon tunnel FET. The minimum subthreshold swing decreased from 146.3 to 21.4 mV/dec and the ON/OFF current ratio increased from 10 7 to 10 13 compared with a normal TFET.INDEX TERMS Band-to-band tunneling (BTBT), fringe-induced barrier lowering (FIBL), subthreshold swing (SS), gate field plate, tunnel field-effect transistor (TFET).

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Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective

Cited by 26 publications

References 24 publications

Output Conductance of Line-TFETs for Different Device Parameters and its Effect on Basic Analog Circuits

Output Conductance of Line-TFETs for Different Device Parameters and its Effect on Basic Analog Circuits

Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET

Gate Field Plate Structure for Subthreshold Swing Improvement of Si Line-Tunneling FETs

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