Drain-Dependence of Tunnel Field-Effect Transistor Characteristics: The Role of the Channel

Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric

“…al. reported drain voltage influence on TFET characteristics [17] predicting an inferior drain-current (saturation) characteristics of gate drain underlap (GDU) structure in comparison to a TFET with full gate (aligned with both source and drain junction). However, when a Hetero gate structure is used for both p-i-n and p-n-p-n, the output characteristics does not change (Fig.…”

“…The later scheme i.e. short gate/gate drain underlap is also effective in reducing the gate-drain capacitance, which is very high in case of TFETs and leads to inferior circuit performance [16], but it has its implications on increasing channel resistance [13] and degrading the output characteristics [17]. Thus, in this work, a gate dielectric engineered Hetero gate (HG) p-i-n and p-n-p-n architecture are taken into consideration, in order to study the impact of gate dielectric modulation on ambipolar behavior and more importantly on the device capacitance characteristics and circuit performance.…”

Mathematical modeling insight of hetero gate dielectric-dual material gate-GAA-tunnel FET for VLSI/analog applications

“…The major roadblock with the planar TFETs is its lower ON-state current (I ON ), which results in lower operating speed. In order to resolve this issue, numerous kinds of TFETs with various structures and materials such as double-gate, delta layer, SiGe, and PNPN structures have been proposed (Toh et al 2007;Boucart and Ionescu 2007a, b;Toh et al 2008;Mallik and Chattopadhyay 2011;Jhaveri et al 2010;Cho et al 2011;Lee et al 2010;Noguchi et al 2015). To enhance the I ON , Silicon nanowire TFET has already been fabricated Abstract This paper presents a mathematical modeling insight for the novel heterogate dielectric-dual material gate-GAA TFET (HD-DMG-GAA-TFET) and validating the results with TCAD simulation.…”

“…(Gandhi et al 2011). Further, a high-k material has been locally inserted (near the source side) in the gate dielectric to form heterogate-dielectric (HD) TFETs (Choi and Lee 2010;Mallik and Chattopadhyay 2011). The presence of high-k dielectric results into a higher band bending due to increase in surface potential (at a constant gate bias) (Jhaveri et al 2010;Lee et al 2012;Madan et al 2015a, b).…”

An Analytical Surface Potential Model of Surrounding Gate Tunnel FET

“…Previous work on analytical modeling of TFET using double gate TFET in [3] indicated or evinced improved result for ON current while OFF current remains in fempto or pico ampere range. Double gate TFET is dependent on drain potential and these new findings is investigated in paper [4]. High gate dielectric and thin film structure boost ON current and the significance of using both in DG TFET is shown in [5,6].…”