DRAM memory electrical yield improvement by backgrinding induced backside damage

Kuo, Kwei-Kuan; Emoto, Shunya; Tabuchi, Tomotaka; Igami, Yukiko

doi:10.1109/emap.2006.4430675

Cited by 2 publications

(1 citation statement)

References 9 publications

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“…But to achieve this incredible quality, manufacturers have to play a lot of tricks with ECC, bad row and column replacement, and so on. The bare yield of the DRAM cells themselves is only around 90% [5]. The memristors surveyed vary a bit in yield, but all fall within a range of 80-95%, which is obviously quite similar to DRAM.…”

Section: Rram Vs Drammentioning

confidence: 98%

Architectural evaluation of 3D stacked RRAM caches

Lewis

Lee

2009

2009 IEEE International Conference on 3D System Integration

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The first memristor, originally theorized by Dr. Leon Chua in 1971, was identified by a team at HP Labs in 2008. This new fundamental circuit element is unique in that its resistance changes as current passes through it, giving the device a memory of the past system state. The immediately obvious application of such a device is in a non-volatile memory, wherein high-and low-resistance states are used to store binary values. A memory array of memristors forms what is called a resistive RAM or RRAM. In this paper, we survey the memristors that have been produced by a number of different research teams and present a point-by-point comparison between DRAM and this new RRAM, based on both existent and expected near-term memristor devices.In particular, we consider the case of a die-stacked 3D memory that is integrated onto a logic die and evaluate which memory is best suited for the job. While still suffering a few shortcomings, RRAM proves itself a very interesting design alternative to well-established DRAM technologies.

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Section: Rram Vs Drammentioning

confidence: 98%