DRAM-on-logic Stack &amp;#x2013; Calibrated thermal and mechanical models integrated into PathFinding flow

Milojevic, Dragomir; Oprins, Herman; Ryckaert, Julien; Marchal, Paul Alfred; Plas, G. Van der

doi:10.1109/cicc.2011.6055357

Cited by 15 publications

(5 citation statements)

References 5 publications

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“…Better a conduction is required via optimized materials of interface (Thermal Materials -TIM Interfaces). The use of wasteful passive layers (heat-spreaders) is common [1][2]: their role is to set out again the heat generated by a hot point on greatest possible surface in order to minimize the impact of it. Finally, the natural and forced improvement of the convections is obtained thanks to active systems like heat sinks or ventilators ( Figure 1) [ 3].…”

Section: Introductionmentioning

confidence: 99%

Study of Miniaturization of a Silicon Vapor Chamber for Compact 3D Microelectronics, via a Hybrid Analytical and Finite Element Method

Shirazy

Struss

et al. 2019

TNC

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The interest in silicon vapor chambers (SVCs) has increased in the recent years as they have been identified as efficient cooling systems for microelectronics. They present the advantage of higher thermal conductivity and smaller form factor compared to conventional heat spreaders. This work aims to investigate the potential miniaturization of these devices, preliminary to integration on the backside of mobile device chips, located as close as possible to hotspots. While detailed numerical models of vapor chamber operation are developed, an easy modeling with low computational cost is needed for an effective parametric study. Based on the study of the operating limits, this paper shows the thinning potential of a water filled micropillar for a device operating below 10 W and identify the corresponding vapour core height, and wick thickness.

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Section: Introductionmentioning

confidence: 99%

Study of Miniaturization of a Silicon Vapor Chamber for Compact 3D Microelectronics, via a Hybrid Analytical and Finite Element Method

Shirazy

Struss

et al. 2019

TNC

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“…In addition to the µbump layout, the design engineers can select the position and the intensity of the heat dissipating structures and the values of certain design parameters such as the thickness of the layers, the interface material and the convection coefficients. The thermal behaviors of different configurations have to be tested and compared, through modeling techniques, in the early design phase, already in the pathFinding phase [3,4], to select the best technology and design options. Finite elements methods (FEMs) are commonly used for this aim.…”

Section: Introductionmentioning

confidence: 99%

Convolution based compact thermal model application to the evaluation of the thermal impact of die to die interface including interconnections

Maggioni

Oprins

Beyne

et al. 2014

Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)

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Thermal aware design of integrated circuits is essential to avoid reliability issues and failures especially in 3D-technology where active dies are placed on top of each other and more heat is dissipated on the same area available for cooling compared to conventional 2D-packages. A certain number of parameters can be selected to reduce temperature and temperature gradient. This paper is mainly focusing on the thermal impact of the dieto-die interface layer. This consists of adhesive material and arrays of interconnection structures. Besides being used for electrical die-die connections, they can be added to locally improve the low thermal conductivity of the adhesive. Short computational time is preferred for the thermal analysis of different designs: this is why various compact thermal models (CTMs) strategies have been developed. The one presented here, for the steady state temperature evaluation of two dies stacks, is based on convolution and fast Fourier transform. A novel correction methodology is introduced to deal with the material non-homogeneity in the interface layer. Case analyses, as the interface material thermal impact or the maximum achieved temperature as a function of the amount of interconnections, are presented in the paper and can be quickly and easily performed with this CTM.

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“…The wide band transmission between the logic and the memory is becoming indispensable for not only mobile products, but also other products related to a network area such as servers and data centers. These days 3D integration with Through Silicon Via (TSV) is considered as the key solution, which brings benefits leading to low power consumptions and downsizing of products [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

“…Especially, to develop effective underfill methods for 3D is unavoidable to relieve mechanical stresses so that the reliabilities of interconnections can be enhanced [7][8][9][10]. However, 3D structure with a thin logic device as a bottom die and Wide I/O DRAM as a top die has a lot of challenges in its assembly process such as: (1) To achieve void less underfill formation under the thin logic die, (2) To prevent underfill resin creeping on the back side of the thin logic die not to affect the memory die stacking, (3) To fill space with the underfill resin under overhangs of the memory die when the memory die is larger than the logic die. To overcome these challenges, Non Conductive Film (NCF) laminated on organic substrates before flip chip bonding was selected as the underfill material in this study.…”

Section: Introductionmentioning

confidence: 99%

High density and reliable packaging technology with Non Conductive Film for 3D/TSV

Ono

Watanabe

Ishikawa

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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The innovative flip chip assembly process with Non Conductive Film (NCF) contributes to high density and reliable 3D/TSV integrations has been developed and demonstrated. The target package had two tier structure which consisted of a logic device and Wide I/O DRAM. The logic device was fabricated by via-middle process and accompanied with 1200 TSVs, a thickness of 50 μm and 40 μm / 50 μm bump pitch layout. Thermalcompression bonding method with Cu pillar was applied to both connections between the memory die and the logic die and between the logic die and an organic substrate so that the high reliability could be achieved. In this work, NCF laminated on substrates was selected as an underfill material to establish robust process for 3D integrations and to realize the cost effective assembly. As reliability test items, 1500-cycle temperature cycling test, 1000h high temperature storage test, 1000h high humidity test, 500h unbiased highly accelerated stress test and 300h pressure cooker test were performed. Furthermore, 28 nm logic device and Wide I/O DRAM were assembled into the 3D structure with this new technology and 12.8 GB/s transmission and 89 % reduction of I/O power compared to LPDDR3 were demonstrated.

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DRAM-on-logic Stack – Calibrated thermal and mechanical models integrated into PathFinding flow

Cited by 15 publications

References 5 publications

Study of Miniaturization of a Silicon Vapor Chamber for Compact 3D Microelectronics, via a Hybrid Analytical and Finite Element Method

Study of Miniaturization of a Silicon Vapor Chamber for Compact 3D Microelectronics, via a Hybrid Analytical and Finite Element Method

Convolution based compact thermal model application to the evaluation of the thermal impact of die to die interface including interconnections

High density and reliable packaging technology with Non Conductive Film for 3D/TSV

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