DRAM reliability characterization by using dynamic operation stress in wafer burn-in mode

Abstract

Capacitor over bitline(C0B)Shallow trench isolation 65A WSixlpoly-Si/SiOz Self-aligned contact (SAC) Direct tungsten ON dielectric 0.15 pm ABSTRACT Circuit to apply the dynamic operation stress (DOS) to DRAM cell in wafer bum-in (WBI) mode is successfully implemented and contributes to characterize the reliability of DRAM in wafer level. We verify that DOS during bum-in(BI) test deteriorates data retention time microscopically, which is mainly attributed to DOSinduced hot carrier (HC) degradation of DRAM cell. In addition, the characterization result of DRAM reliability by DOS-applying method in WBI mode is a good agreement with that by dynamic operation in package hum-in (PBI) mode. [Key words: wafer burn-in, package burn-in, retention time]