DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit

Rajarathnam, Rachel Selina; Alawieh, Mohamed Baker; Jiang, Zixuan; Iyer, Mahesh A.; Pan, David Z.

doi:10.1109/asp-dac52403.2022.9712562

Cited by 9 publications

(4 citation statements)

References 17 publications

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“…Our methodology, which combines the proposed algorithm and GPU acceleration with the VTR framework, focuses on comparing the time required for the packing and placement processes. The GPU acceleration methodology extends the PyTorch and DREAM-Place frameworks [25,26,35]. The included operator (op) layers consist of adjust_node_area, clustering_compatibility, dct, demand_map, density_map, pin_pos, pin_utilization, place_io, precondWL, rmst_wl, rudy, utility, and weighted_average_wirelength.…”

Section: Resultsmentioning

confidence: 99%

“…The DREAMPlaceFPGA framework is currently in its early stages, offering a significant advantage by presenting a generalized solution for GPU-based EDA problems, albeit primarily focused on global placement challenges [26]. The framework encompasses various operators within its op layer, including adjust_node_area, clustering_compatibility, dct, demandMap, density_map, pin_pos, pin_utilization, place_io, precondWL, rmst_wl, rudy, utility, and weighted_average_wirelength.…”

Section: Improvements To the Gpu Acceleration Frameworkmentioning

confidence: 99%

“…In recent years, within the realm of large-scale digital integrated circuit placement research, placement tools based on machine learning methods have begun to emerge [21,22]. These include Google's EDA achievements based on reinforcement learning [23], the RLPlace placement tool based on reinforcement learning [24], and the DREAMPlace and DREAMPlaceFPGA frameworks with GPU acceleration [25,26]. However, at this stage, addressing the entire process from the circuit netlist to placement remains a challenging endeavor, and the exploration of FPGA placement using artificial intelligence methods is still in its nascent stages [21,27].…”

Section: Introductionmentioning

confidence: 99%

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A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

Liu,

Wang,

2023

Electronics

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Field Programmable Gate Arrays (FPGAs), renowned for their reconfigurable nature, offer unmatched flexibility and cost-effectiveness in engineering experimentation. They stand as the quintessential platform for hardware acceleration and prototype validation. With the increasing ubiquity of FPGA chips and the escalating scale of system designs, the significance of their accompanying Electronic Design Automation (EDA) tools has never been more pronounced. The placement process, serving as the linchpin in FPGA EDA, directly influences FPGA development and operational efficiency. This paper introduces an FPGA placement methodology hinging on the Verilog-to-Routing (VTR) framework. We introduce a novel packing approach grounded in the weighted Edmonds’ Blossom algorithm, ensuring that the CLB generation strategy aligns more closely with load-balanced distribution. Furthermore, we enhanced the electric field-driven resolver placement process for CLB locations and leverage GPU-accelerated design. Experimental results demonstrate substantial improvements over the traditional VTR algorithm, with an average optimization of 28.42% in the packing process runtime, an average acceleration ratio of 2.85 times in the placement phase, and a 39.97% reduction in total packing and placement runtime consumption.

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Section: Resultsmentioning

confidence: 99%

Section: Improvements To the Gpu Acceleration Frameworkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

Liu,

Wang,

2023

Electronics

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“…al. [14] presented DREAMPlaceFPGA, an open-source FPGA placement framework that is accelerated and built using the PyTorch deep-learning toolkit. It handles FPGA resource heterogeneity and architecture-specific legality constraints using optimized operators and provides a high-level programming interface in Python.…”

Section: Placementmentioning

confidence: 99%

Unraveling the Integration of Deep Machine Learning in FPGA CAD Flow: A Concise Survey and Future Insights

Ghavami¹,

Shannon²

2023

Preprint

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This paper presents an overview of the integration of deep machine learning (DL) in FPGA CAD design flow, focusing on high-level and logic synthesis, placement, and routing. Our analysis identifies key research areas that require more attention in FPGA CAD design, including the development of open-source benchmarks optimized for end-to-end machine learning experiences and the potential of knowledge-sharing among researchers and industry practitioners to incorporate more intelligence in FPGA CAD decision-making steps. By providing insights into the integration of deep machine learning in FPGA CAD flow, this paper aims to inform future research directions in this exciting and rapidly evolving field.

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OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit

Mai,

Wang,

et al. 2023

2023 IEEE 15th International Conference on ASIC (ASICON)

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DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit

Cited by 9 publications

References 17 publications

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

Unraveling the Integration of Deep Machine Learning in FPGA CAD Flow: A Concise Survey and Future Insights

OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit

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