“…The gate oxide thickness is about 40 nm. The n − drift region is implanted with phosphorus with three doping levels to fabricate three devices denoted by devices A, B, and C. The doping concentrations in the drift region near Si-SiO 2 interface are roughly 6.5×10 16 , 5×10 16 , and 3.5×10 16 cm −3 for devices A, B, and C, respectively. To measure the device characteristics, the drain current (I D ) versus gate voltage (V G ) characteristics are measured under linear-region (with the drain voltage, V D , biased at 0.1 V) and saturation-region (V D =3.3 V) with the source and substrate terminals grounded.…”