Dry-etched silicon-on-insulator waveguides with low propagation and fiber-coupling losses

Solehmainen, Kimmo; Aalto, Timo; Dekker, J.; Kapulainen, Markku; Harjanne, Mikko; Kukli, Kaupo; Heimala, Päivi; Kolari, Kai; Leskelä, Markku

doi:10.1109/jlt.2005.857750

Cited by 34 publications

(22 citation statements)

References 14 publications

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“…The ICP recipe was modified from the STS Advanced Silicon Etch ͑ASE™͒ process. 8 The etch depth was 2.2 m. The variation of the etch depth over the wafer was measured with a profilometer as ±0.1 m. After the etch, a 0.46-m-thick thermal oxide was grown to reduce the roughness of the waveguide sidewalls. During the oxidation, the thickness of the SOI layer decreased to 4.3 m. The oxidation also changed the linewidth, so that the total linewidth change due to the fabrication ͑lithography and oxidation͒ was 0.5 m. This process-induced reduction was compensated for by a corresponding linewidth inflation on the mask.…”

Section: Device Fabricationmentioning

confidence: 99%

Design and fabrication of arrayed waveguide grating multiplexers on silicon-on-insulator platforms

Przyrembel¹,

Kuhlow²,

Solehmainen

et al. 2007

Opt. Eng

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We report on the design, fabrication, and optical characteristics of arrayed waveguide grating ͑AWG͒ devices on silicon-on-insulator ͑SOI͒ platforms to act as multiplexers in a hybridly integrated wavelength division multiplexing ͑WDM͒ transmitter for telecommunications and datacom applications. In order to achieve efficient coupling to laser diodes, SOI layers with 4-m-thick Si were used to form rib waveguides. The AWG devices comprised eight channels with a channel spacing of 200 GHz around a center wavelength at 1550 nm. AWG integration with variable optical attenuators is demonstrated to add channel equalization ability.

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Section: Device Fabricationmentioning

confidence: 99%

Design and fabrication of arrayed waveguide grating multiplexers on silicon-on-insulator platforms

Przyrembel¹,

Kuhlow²,

Solehmainen

et al. 2007

Opt. Eng

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“…The silicon etch was carried out with an inductively coupled plasma etcher by using the patterned oxide as a hard mask. The etch recipe was a modification from the STS Advanced Silicon Etch, as described in [7]. The etch depth was 2 m. After removing the oxide mask, a 1-m-thick thermal oxide was grown on top of the patterned silicon structure to reduce the surface roughness.…”

Section: Fabrication and Measurementsmentioning

confidence: 99%

Adiabatic and Multimode Interference Couplers on Silicon-on-Insulator

Solehmainen

Kapulainen

Harjanne

et al. 2006

IEEE Photon. Technol. Lett.

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Abstract-Adiabatic and multimode interference (MMI) 3-dB couplers based on silicon-on-insulator rib waveguides were fabricated and measured. For testing purposes, pairs of identical couplers were cascaded to form Mach-Zehnder interferometers.The adiabatic couplers showed excess on-chip loss of 0.5 dB, extinction ratio (ER) of 15-20 dB, and a wide spectral range. The MMI couplers processed on the same wafer showed similar loss per coupler, higher ER, and limited spectral characteristics.

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“…18 On the other hand, the top importance for MOEMS (or wave guide) application is the silicon sidewall etching quality. 19,20 If these two requirements can be realized in one etching step, more potential applications in micro-optoelectronic systems integration can be revealed.…”

Section: Introductionmentioning

confidence: 99%

Fabrication of high aspect ratio structure and its releasing for silicon on insulator MEMS/MOEMS device application

Fan

Zhang

Liu

et al. 2015

J. Micro/Nanolith. MEMS MOEMS

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We systematically investigate the fabrication and dry-release technology for a high aspect ratio (HAR) structure with vertical and smooth silicon etching sidewalls. One-hundred-micrometer silicon on insulator (SOI) wafers are used in this work. By optimizing the process parameters of inductively coupled plasma deep reactiveion etching, a HAR (∼25∶1) structure with a microtrench width of 4 μm has been demonstrated. A perfect etching profile has been obtained in which the structures present an almost perfect verticality of 0.10 μm and no sidewall scallops. The root-mean square roughness of silicon sidewalls is 20 to 29 nm. An in situ dry-release method using notching effect is employed after etching. By analysis, we found that the final notch length is typically an aspect-ratio-dependent process. The structure designed in this work has been successfully released by this in situ dry-release method, and the released bottom roughness effectively prohibits the stiction mechanism. The results demonstrate potential applications for design and fabrication of HAR SOI MEMS/MOEMS.

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Dry-etched silicon-on-insulator waveguides with low propagation and fiber-coupling losses

Cited by 34 publications

References 14 publications

Design and fabrication of arrayed waveguide grating multiplexers on silicon-on-insulator platforms

Design and fabrication of arrayed waveguide grating multiplexers on silicon-on-insulator platforms

Adiabatic and Multimode Interference Couplers on Silicon-on-Insulator

Fabrication of high aspect ratio structure and its releasing for silicon on insulator MEMS/MOEMS device application

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