Dry Etching Solutions to Contact Hole Profile Optimization for Advanced Logic Technologies

Wang, Xinpeng; Huang, Yi Ting; Han, Qiu-Hua; Zhang, Haiyang; Lee, Kwok-Fung

doi:10.1149/1.3694338

Cited by 6 publications

(2 citation statements)

References 2 publications

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“…Lower CxFy/O2 ratio could lead to bigger AEI CD, lower contact open risk and lower Oxide-to-CESL selectivity. Condition 3 is the current-best performance [3] .…”

Section: Schemes Of CD Shrinkage In Contact Etch Processmentioning

confidence: 99%

Contact Etch Schemes at Advanced Logic Technology Nodes

2014

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Since CMOS technology moved to sub40nm node and beyond, the limits of both pre-etch and post-etch process have posed the huge challenges to contact etch itself, contact etch is playing a more and more critical role in yield enhancement. In this paper, we addressed the different schemes for both gate-first process and gate-last process to deal with the limits of pre-etch conditions including the ILD (inter-layer dielectrics) thick variation related litho local defocus, the random photo resist footing/scumming, the much thinner ILD thickness on gate, the excessively small pitch related overlay effect and the impact of gate height, and to handle the limits of post-etch processes such as WET clean related polymer remaining and W gap-fill related W missing. In brief, besides the well optimized traditional etch processes to deliver the vertical contact hole, both the pre-etch treatment and the special flush step are indispensable to broaden the overall contact loop process window, reduce the contact open and/or high Rc issue. Both indexes are highly related to final yield performance.

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“…Lower CxFy/O2 ratio could lead to bigger AEI CD, lower contact open risk and lower Oxide-to-CESL selectivity. Condition 3 is the current-best performance [3] .…”

Section: Schemes Of CD Shrinkage In Contact Etch Processmentioning

confidence: 99%

Contact Etch Schemes at Advanced Logic Technology Nodes

2014

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“…Previous studies already showed the contact profile of CESL part also needs to be well controlled to ensure the good profile to avoid the potential contact to gate bridge and less silicide loss performance for the concern of leakage. [6] Silicon loss at the bottom of share contact hole was highlighted as another key issue of junction leakage as shown in Figure 6. This is caused by excessive over-etch percentage of CESL together with the insufficient height and profile of spacer wall.…”

Section: Effect Of Etch Chemistry In Lrm Process On Silicon Loss and ...mentioning

confidence: 99%

Dry Etching Solutions to Contact Etch for Advanced Logic Technologies

Wang

Huang²,

Huang

et al. 2013

ECS Trans.

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Dry Etching Solutions to Contact Etch for Advanced Logic Technologies Heavy polymer and byproducts from CD shrinkage will easily cause contact hole open, especially for the tapered hole profile. The sufficient over-etch without any silicon loss and too much silicide loss is also required to maintain enough process window for less junction leakage. Meanwhile, the circularity of contact hole needs to be well controlled to avoid the potential contact to poly gate bridge issue. In this work, we investigated the impact of dry etching process on contact hole profile and circularity, balanced contact hole CD shrink and contact open issue. Results demonstrate the overall contact hole profile needs to be rigorously controlled by optimizing the etch selectivity of silicon oxide over silicon nitride, the etch treatment is imperative to reduce the contact open issue. The circularity of contact hole can be well improved by tuning the etching chemistry at bottom anti-reflective coating open step and optimizing patterning film stack.

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