To reduce power consumption from gate oxide leakage, Intel Corporation has successfully introduced high-k dielectrics for 45 nm CMOS technology. This paper provides an overview of interface defect response at the high-k dielectric and high-mobility substrate interface. Different passivation methods are discussed, as are their influence on device performance. The impact of the deposition process is also discussed. The influence of deposition parameters, substrate surface orientation, pre-deposition surface treatment, and subsequent annealing temperatures on interface characteristics is presented. The development of high k/Ge and high k/III-V interfaces are also discussed.