Dual-Core Architecture for PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer

Nieto, Rubén; Mateos, R.; Hernández, Álvaro; Diaz, E.

doi:10.1109/etfa.2019.8869476

Cited by 1 publication

(4 citation statements)

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“…respectively. It is worth noting that the results shown for the Zynq® 7000 have been compiled from previous works [28] and [31], and included here for comparison's sake, showing the performance improvement that Zynq® US+ can provide.…”

Section: Resultsmentioning

confidence: 99%

“…Finally, the number of sub-carriers in the FBMC transmultiplexer has been set at M = 512. Table 1 shows the processing times (average value and standard deviation) for the software implementation (channel estimation and equalizer coefficient calculation), as well as the speed-up achieved for the single-core [28] and dual- core approaches [31] in the Zynq® 7000 family, depending on the order L of the ASCET and using the inter-core synchronization method based on atomic instructions (this one is better than the one based on interrupts for this device, as was mentioned before). These results are the average and standard deviation for a thousand realizations of the algorithm.…”

Section: Resultsmentioning

confidence: 99%

“…In [31] both inter-core synchronization methods have been described and evaluated to determine their performance. Fig.…”

Section: A Dual-core Proposalmentioning

confidence: 99%

“…However, in this previous proposal [28], with only one core, the final results did not allow to fulfil the timing constraints defined by the standard, whereas SNR and BER remain comparable with previous works. Finally, a dual-core proposal for Zynq® 7000 has been presented in [31], where the resulting processing times are much shorter, actually divided by a factor x2, thus proving that a mixed HW/SW approach with multiple cores may improve performance figures significantly, while saving hardware resources. In this way, this work becomes an innovative proposal about how to achieve real-time SoC architectures in PLC systems, taking advantage of the full parallelism provided by the different elements existing in current Field-Programmable Gate Array (FPGA) devices, such as multiple cores and specific hardware peripherals designed for the application.…”

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confidence: 99%

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Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution

2020

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Power-Line Communication (PLC) employs multi-carrier modulations, such as Filter-Bank Multi-Carrier (FBMC), to improve communications through the PLC channel and provide an efficient use of the spectrum, thus allowing higher data rates. Since one of the main drawbacks is the noisy channel with multipath and frequency-selective fading, the receiver typically includes a channel estimator and equalizer, at the expense of increasing the computational load and complexity of that receiver and making it difficult to obtain realtime solutions. In this context, this work proposes a heterogeneous System-on-Chip (SoC) architecture for the real-time implementation of a FBMC transmultiplexer that involves the channel estimation and equalization at the reception stage. For that purpose, the performance of a multi-core approach is evaluated for both the Zynq® 7000 SoC and the Zynq® UltraScale+ (US+) devices, by using a single-, dual-and quad-core solution to perform the channel estimation and the calculation of the equalizer coefficients in the ARM processor available in the proposed architecture. Two approaches have been analysed for the necessary synchronization among cores; one based on atomic instructions and the other one on interrupts. The dualcore proposal in both Zynq® 7000 and Zynq® US+ provides a x2 acceleration compared to the single-core proposal, whereas the quad-core one in Zynq® US+ does not provide a x4 acceleration as expected, due to the timing overheads of the synchronization among cores imposed by the data dependencies existing in these tasks. Experimental results include the evaluation of the processing times for each task in the algorithm, as well as the acceleration obtained by each proposal. The proposed architecture can be easily applied to other processing algorithms that may take advantage of the parallelism provided by the multi-core approach in a more efficient way, depending on their data dependencies.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

“…In [31] both inter-core synchronization methods have been described and evaluated to determine their performance. Fig.…”

Section: A Dual-core Proposalmentioning

confidence: 99%

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confidence: 99%

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