Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures

Abstract

SUMMARYThe efficiency of ubiquitous SIMD (Single Instruction Multiple Data) media processors is seriously limited by the bottleneck effect of the scalar kernels in media applications. To solve this problem, a dual-core framework, composed of a micro control unit and an instruction buffer, is proposed. This framework can dynamically decouple the scalar and vector pipelines of the original single-core SIMD architecture into two free-running cores. Thus, the bottleneck effect can be eliminated by effectively exploiting the parallelism between scalar and vector kernels. The dual-core framework achieves the best attributes of both single-core and dual-core SIMD architectures. Experimental results exhibit an average performance improvement of 33%, at an area overhead of 4.26%. What's more, with the increase of the SIMD width, higher performance gain and lower cost can be expected.

Redefining the relationship between scalar and parallel units in SIMD architectures

“…We extends the preliminary work of our previous dualcore framework [7], which is oriented to eliminate scalar kernels' bottleneck effect. However, compared with the dynamic coupling mechanism proposed in this paper, the relationship between SU and PU is not well investigated.…”

“…One characteristic of these scalar kernels is that they are always chained with parallel kernels [7]. Examples includes the Resource Element Mapping with STBC (Space Time Block Code) encoding (STBC+REM) [3], and the IDCT transformation and Quantization kernels with the reordering (IQ+R) [4].…”

“…In the execution of most parallel kernels, PU is kept busy doing intensive computations, while SU stays idle for most of the time. When mapped on the baseline SIMD architecture model described in section IV, two features of SU operations can be concluded from some representative parallel kernels like Fast Fourier Transform (FFT), Space Time Block Code (STBC) encoding Inverse Discrete Cosine Transformation (DCT) and Quantization [7]. One is the simple and type limited feature.…”

B-SCT: Improve SpMV processing on SIMD architectures

“…SIMD processors always contain multiple processing elements (PEs) running in a lock-step manner [1], providing efficient parallel data processing. Thus, the abundant data level parallelism in SpMV makes SIMD processors become the most attracting processing tool.…”