Dual dielectric silicon metal-oxide-semiconductor field-effect transistors as radiation sensors

Abstract

A new design for radiation-sensing field-effect transistors (RADFETs) is presented, involving the use of very thick silicon nitride layers deposited on top of a high-quality thermal silicon dioxide. In contrast to previous RADFET fabrication procedures, no attempt was made to introduce hole traps into the thermal oxide. Instead the trapping layer at the nitride oxide interface was used to store the positive charge which forms the basis for operation of the RADFET. Data is presented which shows hole transport in the thermal oxide. Models explaining the field dependence of the response and the saturation behavior of the dual dielectric device are given. These RADFETs are more stable than any previously described in the literature and have a sensitivity of 86 μV/rad dose at room temperature.

Floating-Gate MOS Transistor with Dynamic Biasing as a Radiation Sensor

“…Thus, threshold voltage is shifted, which is proportional to the absorbed dose. Hughes et al [12] showed that dual dielectric MOS transistor as a radiation sensor increase stability compared with conventional MOS transistor. Silicon nitride layer was deposit on top of high-quality thermal silicon dioxide.…”

Response of a MEMS Microshutter Operating at 60 K to Ionizing Radiation

“…The second is the presence of potential barriers between the Si N and the SiO that effectively block the movement of electrons and holes from Si N into SiO , but not the reverse [9]. Therefore, a positive bias applied to the shutter flap causes the electrons generated in the SiO to move towards the oxide/nitride interface, where most of the electrons will be trapped [10]. Holes in the Si N are immobile at low temperature.…”

Digital radiology using active matrix readout of amorphous selenium: Radiation hardness of cadmium selenide thin film transistors

“…Both the lifetime and mobilities of electrons and holes in Si 3 N 4 are much lower than in SiO 2 , 28 and there are a large number of electron and hole traps existing in Si 3 N 4 which can trap practically all the electrons and holes generated in the SiO 2 layer at the Si 3 N 4 interface. 29 Therefore these two assumptions can be made for the ONO TFTs: ͑i͒ the number of charge carriers generated in Si 3 N 4 was negligible compared to SiO 2 ; ͑ii͒ the fraction of trapping for both electrons and holes at the Si 3 N 4 -SiO 2 interface is unity. Shown in Fig.…”

“…Since the results of this experiment indicate that ⌬V T depends only on the properties of the gate insulator, this could be accomplished using combinations of the following methods: ͑1͒ reducing the gate insulator thickness; ͑2͒ decreasing f T by radiation hardening techniques; ͑3͒ choosing a different gate insulator material, such as Si 3 N 4 , which has a higher dielectric constant and a much larger W Ϯ than SiO 2 . 28,29 A recent study on radiation hardness of a-Si TFTs showed that devices produced with a 200-nm-thick Si 3 N 4 gate insulator were adequate for portal imaging. 8 This approach could possibly be applied to CdSe TFTs.…”