“…Conversely, for the L-filtered inverter, the -R within [1/(4Td), fs/2] is not mitigated [61]. Additionally, the -R also appears within [1/(4Td), fs/2] for the voltage-magnitude emulation by the dual-loop voltage control [60] and the impedance emulation [63]. Thus, reducing time delay is a direct method to mitigate -R. centralized control and the distributed control [12], [49], [53], [54].…”