Dual-Gate Characteristics of Amorphous $ \hbox{InGaZnO}_{4}$ Thin-Film Transistors as Compared to Those of Hydrogenated Amorphous Silicon Thin-Film Transistors

Dual gate indium-gallium-zinc-oxide thin film transistor with an unisolated floating metal gate for threshold voltage modulation and mobility enhancement

“…Under depletion mode operation, dV th can be given as dV th ͓C G C D / C G + C D ͔ =−dV BG C BG . 7 Compared to the conventional dual gate TFT that uses a MOS diode as the back gate, the MS back gate contact in this study leads to a high capacitor ͑C BG ͒. As a result, a small back gate voltage ͑V BG ͒ can shift the V th significantly.…”

“…Double gate TFT is another feasible approach that uses one gate with a constant voltage ͑control gate͒ to change the threshold voltage position during the main gate scanning. 6,7 Double gate TFT can adjust the threshold voltage position in both positive and negative direction. However, the additional power supply to the control gate makes the circuit design complicated.…”

“…Due to the thin active layer ͑e.g., 35 nm͒, the devices are operated with a fully-depleted IGZO body. 6,7 The proposed double gate transistor can be regarded as a composition of three capacitors. They are the capacitor of the bottom main gate ͑C G , which is formed by the gate dielectric͒, the depletion capacitor ͑C D , which is formed by the depleted IGZO body͒ and the capacitor of the back gate ͑C BG , which is formed by the MS backgate contact͒.…”

“…They are the capacitor of the bottom main gate ͑C G , which is formed by the gate dielectric͒, the depletion capacitor ͑C D , which is formed by the depleted IGZO body͒ and the capacitor of the back gate ͑C BG , which is formed by the MS backgate contact͒. 7 In the case of the enhancement mode operation, the channel forms on the dielectric surface and the body is depleted by the back gate. Therefore, the channel is located between C G and C D as shown in the bottom of Fig.…”

High‐Performance Hybrid Complementary Logic Inverter through Monolithic Integration of a MEMS Switch and an Oxide TFT

“…As the bias voltage applied to the top gate became more negative (from -5 V to -10 V), the turn-on voltage of the n-type oxide TFT increased (from -1 V to 3 V) due to the reduction of electrons to be depleted in the channel region. [ 42 ] The n-type oxide TFT showed leakage current of 10 −13 A and an on/off current ratio of 10 5 at 0.1 V drain voltage. After measuring each device's characteristics, we found that the switching characteristics of the n-type oxide TFT were not changed during consecutive MEMS switch integration.…”