Dual injection enhanced planar gate IGBT with self-adaptive hole path for better trade-off and higher SOA capability

Abstract

A novel dual injection enhanced planar gate IGBT with self-adaptive hole path (DIE-PIGBT) is proposed. A floating-P region is applied behind the emitter-connected deep trench in z direction and contacted with the N-type carrier stored (N-CS) layer for the proposed IGBT. Compared to the conventional trench shielded planar gate IGBT (CTS-PIGBT), the proposed device further alleviates the negative impact of the N-CS layer on the breakdown voltage (BV) and reduces both the on-state voltage drop (Vceon) and saturated collector current density (Jsat). Simulation results show that with the same device thickness of 400μm, the BV are 4625V and 4275V for the proposed and conventional device, respectively. The Vceon at 75A/cm2 is 2.51V for the proposed DIE-PIGBT, which is 1.13V lower than that of the CTS-PIGBT. Furthermore, with similar BV to the conventional one, the device thickness can be reduced to 355μm for the DIE-PIGBT. Pro. The total gate charge (QG) and miller plateau charge (QGC) for the proposed device are reduced by 61.0% and 89.9%, respectively. As a result, the proposed structure has better trade-off relationship between the Vceon and turn-off loss (Eoff). At the same Vceon of 2.51V, the Eoff for the DIE-PIGBT and DIE-PIGBT. Pro are 45.17mJ/cm2 and 41.01 mJ/cm2, which is reduced by 44.0% and 49.1% when compared to 80.61mJ/cm2 of the CTS-PIGBT, respectively. Moreover, the Jsat is reduced from 619A/cm2 for the CTS-PIGBT to 368A/cm2 for the DIE-PIGBT under the Vge of 15V. The short-circuit withstand time of the DIE-PIGBT is 1.9 times larger than that of the conventional device.