Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications

Abstract

This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively.

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

“…However, TMR is limited by high area, power and delay overheads [8]. Dual-modular flip-flops based on C-element [30] achieves higher cost efficiency than TMR. For example, BISER [31].…”

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

“…5,6 Since SNUs and/or DNUs in the worst case can lead to systemlevel soft errors, so they can be eliminated by data reloading or online self-recovering using the popular radiation-hardening-bydesign (RHBD) approach (as low-cost circuit-level design solution) and/or layout-based solutions (such as isolation, node spacing increase and guard rings). 7,8 Since a conventional SRAM cell structure, namely 6-transistors (6 T), cannot tolerate various kinds of node upsets, 9,10 so far, several designs of SRAM cells have been proposed by designers of integrated circuit (IC) chips through the RHBD approach to mitigate SNUs and MNUs. So far, various differential (dual) and single bitline radiation hardened SRAM cells have been published by researchers which can tolerate SNUs and MNUs, in typical types (based on basic structure in radiation hardened memory cells such as dual interlocked storage cell (DICE), 11 Quatro, 12 ), terrestrial (low-orbit) and aerospace (highorbit) applications using RHDB and layout approaches.…”

“…So far, various differential (dual) and single bitline radiation hardened SRAM cells have been published by researchers which can tolerate SNUs and MNUs, in typical types (based on basic structure in radiation hardened memory cells such as dual interlocked storage cell (DICE), 11 Quatro, 12 ), terrestrial (low-orbit) and aerospace (highorbit) applications using RHDB and layout approaches. [13][14][15][16][17][18][19][20][21][22][23][24][25] In the literature, 19,20 some asymmetrical hardened SRAM cells, where some symmetrical bitline hardened SRAM cells in literatures, [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21] are proposed. Also, single bitline (or single-ended) hardened SRAM cells based on Muller C-elements are proposed in referances.…”