Dual-Page Checkpointing

Abstract

Data persistence is necessary for many in-memory applications. However, the disk-based data persistence largely slows down in-memory applications. Emerging non-volatile memory (NVM) offers an opportunity to achieve in-memory data persistence at the DRAM-level performance. Nevertheless, NVM typically requires a software library to operate NVM data, which brings significant overhead. This article demonstrates that a hardware-based high-frequency checkpointing mechanism can be used to achieve efficient in-memory data persistence on NVM. To maintain checkpoint consistency, traditional logging and copy-on-write techniques incur excessive NVM writes that impair both performance and endurance of NVM; recent work attempts to solve the issue but requires a large amount of metadata in the memory controller. Hence, we design a new dual-page checkpointing system, which achieves low metadata cost and eliminates most excessive NVM writes at the same time. It breaks the traditional trade-off between metadata space cost and extra data writes. Our solution outperforms the state-of-the-art NVM software libraries by 13.6× in throughput, and leads to 34% less NVM wear-out and 1.28× higher throughput than state-of-the-art hardware checkpointing solutions, according to our evaluation with OLTP, graph computing, and machine-learning workloads.

DONUTS: An efficient method for checkpointing in non‐volatile memories

“…These works use logging hardware to generate log entries and coordinate data write‐backs in the background, overlapping persistence with execution. These log procedures can be managed by the load/store unit, 25 the coherence controller, 42 the cache controller, 15,19,21,23,27,43 or the memory controller 1,9,44 …”

“…However, its model tends to multiply the number of writes on NVM and generate more significant traffic between processor and memory, consequently increasing bandwidth use. Dual‐page checkpointing 1 implements a shadow‐paging mechanism to store execution and checkpoint data separately. For mapping, it uses a vector of bits to denote dirty cache lines and their locations on any physical page.…”

“…Non‐volatile memory* (NVM) is a technology emerging as a new memory hierarchy component 1,2 . By providing data persistence with access latency comparable to DRAM but with lower power consumption and higher storage density, many works have used NVM as main memory, either to increase or completely replace DRAMs 3 .…”

“…Projects proposed in the literature to ensure crash consistency in NVM systems have used different approaches, such as shadow‐paging, 1,29 out‐of‐place updates, 3 but the most common is write‐ahead logging (WAL), subdivided into undo‐logging or redo‐logging techniques. In summary, redo‐logging allows recovery to a consistent state by redoing pending operations, while undo‐logging recovers by returning incomplete updates to consistent state values.…”

Compiler-support for Critical Data Persistence in NVM

“…ReDU is a redo logging hardware-assisted technique that dedicates a part of the RAM to serve as a write cache for the NVM, moving these expensive operations away from the critical path [22]. Another hardwarebased data persistence for NVMs is a memory controller that reduces the amount of metadata, and the number of excessive writes is presented in Reference [53]. Data security in addition to persistence are the concerns of SuperMem [58], a programmer-and compiler-transparent hardware system.…”