Dual-path linearization technique for bandwidth enhancement in SAH circuits

Kazeminia, Sarang; Shahsavar, Amir Laal

doi:10.1016/j.aeue.2019.152864

Cited by 5 publications

(1 citation statement)

References 22 publications

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“…In Kazeminia and Shahsavar (2019) a sample and hold circuit for high-speed ADC was proposed. The proposed solution replaced the conventional bootstrapped switching system with the source followers stages for achieving high resolution.…”

Section: Literature Workmentioning

confidence: 99%

Energy and time-efficient circuitry of bat-bootstrap and comp-lifier for ultra-low power SAR-ADC

Faheem

Zhong

Azeem

et al. 2021

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Purpose Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs. Design/methodology/approach To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library. Findings The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively. Originality/value Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

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Section: Literature Workmentioning

confidence: 99%