2020
DOI: 10.1109/access.2020.3009967
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Dual PN Source/Drain Reconfigurable FET for Fast and Low-Voltage Reprogrammable Logic

Abstract: Schottky junction reconfigurable FETs suffer from limited output currents to drive the following stages, jeopardizing their viability for high-end applications. This drawback becomes dramatic at low voltages. In this work, an analogous novel low-bias reprogrammable device is presented. It features a dual PN doping at source and drain which improves the driving current density thanks to the presence of both electron and hole reservoirs within the same structure. 3D-TCAD results for this innovative device on adv… Show more

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Cited by 11 publications
(2 citation statements)
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“…In electronic circuits, logical states are defined as the electrical states within circuit components, which are typically represented by "0" and "1" to indicate the results of logical operations 1,2 . These logical states are realized through engineering of fundamental device structures, such as p-n diodes or metal-oxide-semiconductor field-effect transistors (MOSFETs) 3,4 . Various types of logical gates, such as "AND", "OR", "NAND", "NOT", and "NOR", are used for sophisticated computing tasks by interconnecting individual logical units 5 .…”
Section: Introductionmentioning
confidence: 99%
“…In electronic circuits, logical states are defined as the electrical states within circuit components, which are typically represented by "0" and "1" to indicate the results of logical operations 1,2 . These logical states are realized through engineering of fundamental device structures, such as p-n diodes or metal-oxide-semiconductor field-effect transistors (MOSFETs) 3,4 . Various types of logical gates, such as "AND", "OR", "NAND", "NOT", and "NOR", are used for sophisticated computing tasks by interconnecting individual logical units 5 .…”
Section: Introductionmentioning
confidence: 99%
“…For increasing the forward current, the PG has to be biased at a higher voltage, which causes an increasing potential difference between the CG and the PG when the CG is at low potential or reverse bias, resulting in the generation of leakage and the increase in power consumption, especially when the distance between the PG and the CG is reduced to a deep nanoscale. A complementary doped S/D bidirectional RFET (CD-BRFET) that is with a dual doping source and drain located next to each other is proposed, 19 it significantly reduces the required voltage of the PG, and the on-state current is also improved. However, compared with the mainstream CMOS technology today with only a single gate, the additional PG makes metal interconnection more complicated and difficult.…”
Section: Introductionmentioning
confidence: 99%