Current research in small animal positron emission
tomography (PET) scanners focus on obtaining better spatial
resolution and higher sensitivity. These enhancements of scanner
performance result in a corresponding increase in the complexity of
the electronics, which usually manifests through an increase in the
number of electronics channels. Analog-to-digital converters (ADCs)
implemented in field programmable gate arrays (FPGAs) are an
effective way to simplify electronics complexity. In this paper, a
resource-saving multicycle-encoding structure of an FPGA-based ADC
with automated calibration is proposed, which achieves a sampling
rate of 250 Msps. A digitizer module prototype containing 64 charge
measurement channels based on the FPGA ADC is designed using a
Kintex-7 FPGA. The effective number of bits (ENOB) achieved using
the FPGA ADC is 4.26 bits under a 10.0555 MHz sine wave input. The
charge measurement resolution of each channel is better than
5‰ full width half maximum under a 0.8 V signal
input and 3% under inputs in the range 0.1 V to 1.2 V. The
integral nonlinearity of each channel is within ± 1%.