Dual-V<inf>th</inf> based double-edge explicit-pulsed level-converting flip-flops

Data branch sharing dual‐edge explicit‐pulsed level converting flip‐flops

“…Figure 5 shows another proposed static level converting flip-flop (SLCFF). 12 The SLCFF uses a small keeper transistor MP3 to prevent node X from becoming floated if the input signal D remains high during the presence of the pulse. Transistor MP1 is controlled by the input signal D. Node X remains low as long as the input signal D is high.…”

“…The LCFF based on pass‐transistor logic (LCFFBPT) 12 is shown in Figure 4, which employs the feedback devices MP1 and MP3 to reduce the capacitive load (gate capacitance of the keeper device) at node V. However, when the input signal D changes from high to low during the presence of the pulse, the pull‐up and pull‐down branches of node V turn on simultaneously. Therefore, the pull‐down branch needs to be strong enough to overcome the pull‐up branch, which increases the power consumption and delay of the flip‐flop.…”

“…Figure 5 shows another proposed static level converting flip‐flop (SLCFF) 12 . The SLCFF uses a small keeper transistor MP3 to prevent node X from becoming floated if the input signal D remains high during the presence of the pulse.…”

“…[4][5][6][7][8] Although several LCFFs have been proposed in the existing literature, there are still some drawbacks. [9][10][11][12][13] For instance, the required number of transistors is excessive, the power consumption is too large, and the delay is relatively high. To solve the above issues, in this paper, we propose two data branch sharing dual-edge explicit-pulsed level converting flip-flops (DBS-LCFF).…”

“…Although several LCFFs have been proposed in the existing literature, there are still some drawbacks 9–13 . For instance, the required number of transistors is excessive, the power consumption is too large, and the delay is relatively high.…”