Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

Rostami, Masoud; Mohanram, Kartik

doi:10.1109/tcad.2010.2097310

Cited by 75 publications

(45 citation statements)

References 31 publications

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“…The SG/IG modes of operation have been exploited to perform leakage-delay trade-offs [Kumar et al 2004;Chiang et al 2005;Tawfik and Kursun 2007;Rostami and Mohanram 2011;Alioto 2011]. Gate sizing and use of multiple supply/threshold voltages have been studied in the context of power optimization of FinFET circuits [Swahn and Hassoun 2006;Muttreja et al 2007;Ouyang and Xie 2008;Mishra et al 2009].…”

Section: Related Workmentioning

confidence: 99%

3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations

Chaudhuri

Jha

2014

J. Emerg. Technol. Comput. Syst.

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Recently, multigate transistors have been gaining attention as an alternative to conventional MOSFETs. Superior gate control over the channel, smaller subthreshold leakage, and reduced susceptibility to process variations are some of the key features that give multigate structures a competitive edge over MOSFETs. Among various multigate structures, silicon-on-insulator (SOI) FinFETs are promising, owing to their ease of fabrication. However, characterization of SOI FinFET devices/gates needs immediate attention in order for them to gain greater popularity in this decade. Ideally, 3D device simulation should be done for accurate circuit analysis. However, this is impractical due to the huge CPU time required. As a possible alternative, simulating a 2D crosssection of the device yields 10× to 100× reduction in CPU time. However, this introduces significant error in the range of 7% to 20% when evaluating the on/off current (I ON /I OF F ) for a single device and leakage current or propagation delay (I LEAK /t D ) for logic gates.In this work, we first present a methodology to obtain optimized 3D device simulation models for SOI FinFETs. Based on these 3D models, we develop adjusted 2D models to capture 3D simulation accuracy with 2D simulation efficiency. We report results for the 22nm SOI FinFET technology node. We adjust gate underlap (L UN ) in the 2D cross section of the n/pFinFET devices in order to mimic 3D device behavior. When the adjusted 2D models are employed in mixed-mode simulation of FinFET logic gates, the error in the evaluation of I LEAK /t D is very small. To the best of our knowledge, this is the first such attempt. We show that 2D device models remain valid even under process, voltage, and temperature (PVT) variations. We target process variations in gate length (L G ), fin thickness (T SI ), gate oxide thickness (T OX ), and gate workfunction ( G ), which are the parameters that have been shown to have the most impact on leakage and delay.

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Section: Related Workmentioning

confidence: 99%

3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations

Chaudhuri

Jha

2014

J. Emerg. Technol. Comput. Syst.

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“…Application of logic gates includes from small decision making devices, big calculating devices to huge super computers [3,4]. There are many logic gates to implement various Boolean logics among which two gates are considered universal.…”

Section: Introductionmentioning

confidence: 99%

Comparative Study of Various Gates Based in Different Technologies

Chouhan¹,

Chaudhary²,

Upadhay³

et al. 2017

IRATJ

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This paper provides the comparative study among various fabrication technologies for the same logical circuits based on NAND gate. The tool used for this analysis is Tanner which is an EDA tool and used for full custom designing of electronic circuits. The NAND gate is formed by CMOS only. The different technologies give varied output parameters with given input parameters. Hence, the main utilization of this study is to opt best suited technology for particular output parameter ranges for specified input parameter ranges for different applications based on logical gates. The conventional device generally used, consumes high power and is not stable with frequency variations. Therefore, a comparative analysis using different technologies is proposed, which has been useful for designing optimal conventional logics. The study is based on simulation of power consumption, noise analysis and frequency compensation technique of different gates.

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“…Thus, various companies have already announced their intention to switch to FinFETs at the upcoming technology nodes. Although work on power/thermal analysis and optimization of FinFET circuits Chiang et al 2005;Choi et al 2007;Datta et al 2007;Gu et al 2008;Kumar et al 2004;Mishra et al 2009Muttreja et al 2007;Ouyang and Xie 2008;Pacha et al 2007; Rostami and Mohanram 2011;Swahn and Hassoun 2006;Tawfik and Kursun 2008;Xiong and Bokor 2003] and FinFET fault models [Simsir et al 2010] have been presented, thermal characterization of FinFET circuits under test has not been considered.…”

Section: Introductionmentioning

confidence: 99%

Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits

Tang

Jha

2013

J. Emerg. Technol. Comput. Syst.

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Power consumption has become a very important consideration during integrated circuit (IC) design and test. During test, it can far exceed the values reached during normal operation and, thus, lead to temperatures above the allowed threshold. Without appropriate temperature reduction, permanent damage may be caused to the IC or invalid test results may be obtained. FinFET is a double-gate field-effect transistor (DG-FET) that was introduced commercially in 2012. Due to the vertical nature of FinFETs and, hence, weaker ability to dissipate heat, this problem is likely to get worse for FinFET circuits. Another technology rapidly gaining popularity is 3D IC integration. Unfortunately, the compact nature of a multidie 3D IC is likely to aggravate the temperature-during-test problem even further. Hence, before temperature-aware test methodologies can be developed, it is important to thermally analyze both FinFET and 3D circuits under test.In this article, we present a methodology for thermal characterization of various test techniques, such as scan and built-in self-test (BIST), for FinFET and 3D ICs. FinFET thermal characterization makes use of a FinFET standard cell library that is characterized with the help of the University of Florida doublegate (UFDG) SPICE model. Thermal profiles for circuits under test are produced by ISAC2 from University of Colorado for FinFET circuits and HotSpot from University of Virginia for 3D ICs. Experimental results indicate that high temperatures result under BIST and much less often under scan, and that both power consumption and test application time should be reduced to lower the temperature of circuits under test, just reducing the power consumption is not enough.

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Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

Cited by 75 publications

References 31 publications

3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations

3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations

Comparative Study of Various Gates Based in Different Technologies

Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits

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