Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement

Tao, Meng; Dong, Hongbiao; Wang, Tong; Xu, Chong‐Yu

doi:10.1109/date.2010.5457149

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010) 2010

DOI: 10.1109/date.2010.5457149

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Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement

Meng Tao¹,

Hongbiao Dong²,

Tong Wang³

et al.

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Cited by 2 publications

References 7 publications

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Comparative Analysis of Low Power and Low Leakage Reduction for Logic Circuits

Agarwal¹,

Agrawal²

2015

IJEER

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As technology scales in nanometer regime leakage current are becoming important metric of comparable importance to leakage current for the analysis and design of complex logic circuits. In this paper, we did the comparative analysis of leakage current for carry look ahead logic circuits. The simulation results depicts that the proposed design leads to efficient in terms of standby leakage power. We have performed simulations using Cadence Spectra 90nm standard CMOS technology at room temperature with supply voltage of 1V.

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Comparative Analysis of Low Power and Low Leakage Reduction for Logic Circuits

Agarwal¹,

Agrawal²

2015

IJEER

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show abstract

Design of Low Leakage Arithmetic Logic circuit Using Efficient Power Gating Schemes

Kulshethra

Kule²

2019

IJEER

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As technology scales towards nanometer regime the leakage power consumption emerging as a major design constraint for the analysis and design of complex arithmetic logic circuits. In this paper, comparative analysis of standby leakage current and sleep to active mode transition leakage current has been done. An innovative power gating approaches is also analyzed which targets maximum reduction of major leakage current. To analyze we introduce the stacking power gating scheme, we implemented this scheme on carry look ahead adder circuit and then simulation has been done using stacking power gating scheme with 45nm technology parameters. The simulation results by using this scheme in BPTM 45nm technology with supply voltage of 0.9V at room temperature shows that leakage reduction can be improved by 47.14% as on comparison with single transistor gating scheme on comparing with conventional scheme Also, another novel approach has been analyzed with diode based stacking power gating scheme for further reduction in leakage power. The simulation results depicts that the analyzed design leads to efficient carry look ahead adder circuit in terms of leakage power, active power and delay.

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Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement

Cited by 2 publications

References 7 publications

Comparative Analysis of Low Power and Low Leakage Reduction for Logic Circuits

Comparative Analysis of Low Power and Low Leakage Reduction for Logic Circuits

Design of Low Leakage Arithmetic Logic circuit Using Efficient Power Gating Schemes

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