Dual work function metal gate CMOS technology using metal interdiffusion

Polishchuk, I.; Ranade, P.; King, Tsu‐Jae; Hu, Chenming

doi:10.1109/55.944334

Cited by 171 publications

(52 citation statements)

References 7 publications

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“…(6) and ) ap in eq. (11) are in the form of linear and inverse functions of temperature, respectively, they show the same temperature dependency () b (T) and ) ap increase with increasing temperature).…”

Section: )mentioning

confidence: 91%

“…Generally, since Ni has a high work function (5.15 eV), it has been widely employed to form Ohmic contact to p-type semiconductor. 10,11) For a comparison, Ti Schottky contacts to p-type bulk Si were fabricated using same process conditions. The temperature-dependent IV measurements were performed using a precision semiconductor parameter analyzer (Agilent 4156C).…”

Section: Methodsmentioning

confidence: 99%

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Temperature Dependency of Schottky Barrier Parameters of Ti Schottky Contacts to Si-on-Insulator

et al. 2013

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We have investigated the temperature-dependent currentvoltage (IV) characteristics of Ti Schottky structure on the Si-on-insulator (SOI) in the temperature range of 175375 K by steps of 25 K. As decreasing temperature, the barrier height and ideality factor of Ti/SOI Schottky contact were found to be decreased and increased, respectively, indicating a considerable deviation from the ideal thermionic emission model in its current conduction mechanism. From the linear relationship between the barrier heights and ideality factors, the homogeneous barrier height was calculated to be 0.76 eV. The mean barrier height of 0.87 eV and the modified Richardson constant value of 30.63 A·cm ¹2 ·K ¹2 were obtained using modified Richardson plot. On the basis of a thermionic emission mechanism with a Gaussian distribution of the barrier heights, the temperature-dependent IV behavior of Ti/SOI Schottky contact was explained in terms of barrier height inhomogeneities at the interface between Ti and SOI.

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Section: )mentioning

confidence: 91%

Section: Methodsmentioning

confidence: 99%

Temperature Dependency of Schottky Barrier Parameters of Ti Schottky Contacts to Si-on-Insulator

et al. 2013

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“…In terms of the HMG MOSFET fabrication process, several integration schemes have been suggested such as tilt angle evaporation metal gate deposition [16], metal interdiffusion techniques [17] and a metal wet etch process to selectively remove the first metal gate before depositing the second metal [18,19]. Moreover, in 2012, Cao and Ionescu have successfully fabricated duallateral -gate CNTFET with precise positioning DEP method for fabricating self -aligned suspended -body CNFETs efficiently controlled by two laterally placed independent gates with sub -100 nm gate/channel distance [20].…”

Section: Cntfetmentioning

confidence: 99%

Investigation of Hetero - Material - Gate in CNTFETs for Ultra Low Power Circuits

Wang¹,

Xu²,

Liu³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-An extensive investigation of the influence of gate engineering on the CNTFET switching, high frequency and circuit level performance has been carried out. At device level, the effects of gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. It is revealed that hetero -material -gate CNTFET(HMG -CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, and is more suitable for use in low power and high frequency circuits. At circuit level, using the HSPICE with look -up table(LUT) based Verilog -A models, the performance parameters of circuits have been calculated and the optimum combinations of Ф M1 /Ф M2 /Ф M3 have been concluded in terms of power consumption, average delay, stability, energy consumption and power -delay product(PDP). We show that, compared to a traditional CNTFETbased circuit, the one based on HMG -CNTFET has a significantly better performance (SNM, energy, PDP). In addition, results also illustrate that HMG -CNTFET circuits have a consistent trend in delay, power, and PDP with respect to the transistor size, indicating that gate engineering of CNTFETs is a promising technology. Our results may be useful for designing and optimizing CNTFET devices and circuits.

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“…The fabrication of TRC structure is feasible by implementing the fabrication process used by Xiao-Hua et al [16] and Seo et al [17] for grooved gate MOSFET. Further, for GME architecture, many fabrication schemes has been suggested such as inter diffusion process [18,19] and tilt angle evaporation (TAE) [20,21] which makes the fabrication possible even in sub-100 nm regime. Moreover, for the viability of advanced multi-layered gate engineered structures, several techniques [22,23] were reported in the past, using the stack of a thin SiO 2 and a thick high-k layer.…”

Section: Fabrication Feasibility Of Gme-trc Mosfetmentioning

confidence: 99%

Linearity-Distortion Analysis of GME-TRC MOSFET for High Performance and Wireless Applications

Malik¹,

Gupta²,

Chaujar³

et al. 2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: g m1 , g m2 , g m3 , and figure-of-merit (FOM) metrics; V IP2 , V IP3 , IIP3 and 1-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth (X j ) or negative junction depth (NJD) have been examined for GME-TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

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Dual work function metal gate CMOS technology using metal interdiffusion

Cited by 171 publications

References 7 publications

Temperature Dependency of Schottky Barrier Parameters of Ti Schottky Contacts to Si-on-Insulator

Temperature Dependency of Schottky Barrier Parameters of Ti Schottky Contacts to Si-on-Insulator

Investigation of Hetero - Material - Gate in CNTFETs for Ultra Low Power Circuits

Linearity-Distortion Analysis of GME-TRC MOSFET for High Performance and Wireless Applications

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