Dummy Poly Gate Removal Scheme at FinFET

Abstract

High-K metal gate (HKMG) approach has been introduced to enhance the device performance via lowering device current leakage. Dummy poly gate removal (DPGR) process is introduced in HKMG process to form the metal gate with different work functions for n/p-MOS. However, the introduction of this technology does pose many new challenges to various fabrication processes, especially for etch process at 14nm node and beyond. In FinFET technology, ploy-si is removed simultaneously for both n-MOS and p-MOS. normally, the partial dry etch and partial wet etch scheme is adopted for less plasma damage. This paper will introduce full dry etch process to complete poly-si removal. This definitely requires soft etch process to avoid the damage of Fin top and channel while meeting all the physical targets.

Abnormal Silicon Etching Behaviors in Nanometer-Sized Channels

“…14 Engineers have discovered that debris left behind at a small gate width cannot be removed even after a reasonably long wet etching duration. 15 The unstripped debris prohibits metal gate adhesion and induces permanent failure of the device. The potential causes of this unstripping phenomenon have been reported previously, and many hypotheses have been postulated.…”

“…During this replacement gate (RPG) or gate-last step of FET fabrication, the process of eliminating silicon pillars surrounded by dielectric spacers faces the unstripping phenomenon when the feature size is extremely reduced . Engineers have discovered that debris left behind at a small gate width cannot be removed even after a reasonably long wet etching duration . The unstripped debris prohibits metal gate adhesion and induces permanent failure of the device.…”