Duty Cycle Detection Method for High Speed Input-Output Systems

Abstract

A clock coupled duty cycle detection method for high speed input-output is presented in this paper. In High speed systems duty cycle (DC) of output signal needs to be calibrated at 50% for having acceptable performance in the system. The proposed method introduces a synchronous signal in the output of system with 50% duty cycle with maximum 1 % error over process, voltage, and temperature (PVT). Proposed method also compensate input referred offset of DC detector which helps to improve overall system performance. The duty cycle detection method was implemented in 16nm technology with a power supply of 1.2V. With this type of designed architecture, the circuit can provide up to 5Gbps frequency data signal. Experimental results show that proposed architecture is reliable, and it can work operative in high frequency intervals. The presented circuit can be implemented in special serial links of several standards such as Peripheral Component Interconnect (PCI), Universal Serial Bus (USB) and Double Data Rate (DDR).