DVBS2 System Using SDR in Hardware-in-Loop Mode

Abstract

Digital Video Broadcasting-Satellite 2 nd generation (DVBS2) is one of the popular source of entertainment in today's world. It has made TV viewing superb experience due to its ability of sharing high quality picture (i.e. High Definition). But the satellite channel basically follows AWGN type of response as there is lesser chances of multipath generation. The following paper deals with the implementation of the DVBS2 system in Software Defined Radio (SDR) platform and further analysis of its performance both in terms of bit error rate (BER) and actual multimedia transfer capability over different channel conditions like AWGN, and also under multipath condition i.e. Rician channel. All the analysis in the paper is done in hardware-in-loop mode.

A Novel Interactive Communication System Realization through Smart Low Noise Block Downconverter

“…The BitInterlever model is to implement the bit level interlever or deinterleaver for 8PSK, 16APSK, and 32APSK modulation formats. The interleaver is disabled in case of QPSK [17], and the output is directly connected with the input. Each firing, N ldpc bits output tokens are generated and N ldpc bits input tokens consumed.…”