2013
DOI: 10.1016/j.apradiso.2013.08.001
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Dyadic wavelet for image coding implementation on a Xilinx MicroBlaze processor: Application to neutron radiography

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Cited by 4 publications
(4 citation statements)
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“…The aim of this section is to describe a hardware accelerator based on the Gabor filter. The proposed architecture is composed by Microblaze soft-core processors interfaced with shared memory using the AXI4 bus [46]. All processor elements, on-chip memories, and the AXI4 bus are clocked at 100 MHz.…”
Section: Experiments Resultsmentioning
confidence: 99%
“…The aim of this section is to describe a hardware accelerator based on the Gabor filter. The proposed architecture is composed by Microblaze soft-core processors interfaced with shared memory using the AXI4 bus [46]. All processor elements, on-chip memories, and the AXI4 bus are clocked at 100 MHz.…”
Section: Experiments Resultsmentioning
confidence: 99%
“…Saadi et al [19] proposed a mixed software/hardware implementation of 2-D signals encoder/decoder utilizing dyadic DWT in light of quadrature mirror filters utilizing quick wavelet Mallat's algorithm. This work was composed and aggregated on the embedded development kit EDK6.3i and the synthesis software ISE6.3i, which was accessible with Xilinx Virtex-IIV2MB1000 FPGA.…”
Section: Related Workmentioning
confidence: 99%
“…In 2013, Saadi et al [16] proposed a mixed software/hardware implementation of 2-D signals encoder/ decoder utilizing dyadic DWT in light of quadrature mirror filters utilizing quick wavelet Mallat's algorithm. This work is composed and aggregated on the embedded development kit EDK6.3i and the synthesis software ISE6.3i, which is accessible with Xilinx Virtex-IIV2MB1000 FPGA.…”
Section: Literature Reviewmentioning
confidence: 99%