Dynamic Backward Rewriting

Mahzoon, Alireza; Große, Daniel; Drechsler, Rolf

doi:10.1007/978-3-031-24571-8_6

Cited by 2 publications

(4 citation statements)

References 3 publications

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“…Several methods targeting specific problems and different abstraction levels have been proposed [13]. For example, this includes natural language techniques to derive assertions from specifications [14], feature localization in ESL models [15] or in RTL descriptions [16], assertion mining at RTL [17], identification of instruction pipelines using static analysis on the netlist [18], template-based understanding of circuit components [19], and reverse engineering at the gatelevel [20], [21]. However, all these solutions focus on dedicated design understanding sub-problems and do not provide a generic user-programmable analysis for waveforms.…”

Section: Related Workmentioning

confidence: 99%

WAVING Goodbye to Manual Waveform Analysis in HDL Design With WAL

Klemmer,

Große

2024

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Starting points for design understanding and debugging of a Hardware Description Language (HDL) design are generated waveforms. However, waveform viewing is still a highly manual and tedious process, and unfortunately, there has been no progress for automating the analysis of waveforms. Therefore, we introduce the Waveform Analysis Language (WAL) in this paper. WAL allows to create and execute analysis programs on waveforms. We have realized WAL as a Domain Specific Language (DSL). This design choice has many advantages ranging from a natural expressiveness of a waveform analysis problem to providing an Intermediate Representation (IR) well-suited as a compilation target from other languages.We demonstrate the capabilities of WAL in four case studies, covering the analysis of hardware performance of different RISC-V processors, combined hardware/software profiling, the usage of WAL to analyze bus transactions, and the implementation of a new embedded DSL using WALs macro system.

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Section: Related Workmentioning

confidence: 99%

WAVING Goodbye to Manual Waveform Analysis in HDL Design With WAL

Klemmer,

Große

2024

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Section: Mismatchmentioning

confidence: 99%

“…In general, formal multiplier verification is challenging, especially for structurally complex designs such as Booth multipliers [7], [16], [21]. Symbolic computer algebra (SCA) has been successfully employed to verify a variety of integer multipliers [7], [13], [16], [17], [26], which relies heavily on detecting full adders (FAs) and half adders (HAs) in multiplier netlists. The state-of-the-art implementation in ABC framework [26] develops a fast algebraic rewriting approach to extracting adder trees from flattened multiplier netlists by detecting pairs of XOR and MAJ functions, which can handle large bitwidth multipliers (up to 2048-bit) but with extremely long runtime.…”

Section: Mismatchmentioning

confidence: 99%

“…Reasoning high-level abstractions from bit-blasted Boolean networks (BNs) such as gate-level netlists has demonstrated its wide applications in improving functional verification efficiency [7], [16] and identifying malicious logic such as detecting hardware trojan and intellectual property infringement usage [3], [14]. In the era of globalization and democratization of integrated circuit (IC) development and fabrication, such reasoning is expected to bring broader impacts on hardware security, which is at the heart of modern computing systems: more than 40 percent of FPGA/ASIC projects are working under safety-critical development process standards or guidelines [9].…”

Section: Introductionmentioning

confidence: 99%

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Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks

Wu¹,

Li²,

Hao³

et al. 2023

Preprint

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Reasoning high-level abstractions from bit-blasted Boolean networks (BNs) such as gate-level netlists can significantly benefit functional verification, logic minimization, datapath synthesis, malicious logic identification, etc. Mostly, conventional reasoning approaches leverage structural hashing and functional propagation, suffering from limited scalability and inefficient usage of modern computing power. In response, we propose a novel symbolic reasoning framework exploiting graph neural networks (GNNs) and GPU acceleration to reason high-level functional blocks from gate-level netlists, namely GAMORA, which offers high reasoning performance w.r.t exact reasoning algorithms, strong scalability to BNs with over 33 million nodes, and generalization capability from simple to complex designs. To further demonstrate the capability of GAMORA, we also evaluate its reasoning performance after various technology mapping options, since technology-dependent optimizations are known to make functional reasoning much more challenging. Experimental results show that (1) GAMORA reaches almost 100% and over 97% reasoning accuracy for carry-save-array (CSA) and Boothencoded multipliers, respectively, with up to six orders of magnitude speedups compared to the state-of-the-art implementation in the ABC framework; (2) GAMORA maintains high reasoning accuracy (>92%) in finding functional modules after complex technology mapping, upon which we comprehensively analyze the impacts on GAMORA reasoning from technology mapping 1 .

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Dynamic Backward Rewriting

Cited by 2 publications

References 3 publications

WAVING Goodbye to Manual Waveform Analysis in HDL Design With WAL

WAVING Goodbye to Manual Waveform Analysis in HDL Design With WAL

Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks

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