Dynamic clock management for low power applications in FPGAs

Brynjolfson, I.; Žilić, Željko

doi:10.1109/cicc.2000.852635

Cited by 31 publications

(15 citation statements)

References 9 publications

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“…The DPCM [7] is capable of performing dynamic frequency division without undesired effects at the output (such as glitches, distortions, asymmetry, transient frequencies and additional clock edges). As a result, clean frequency changes can take effect within a clock cycle.…”

Section: B Phase-picking Algorithm and Implementationmentioning

confidence: 99%

Design and Performance of 155 Mbps Clock/Data Recovery Circuits on Heavy Loaded PLDs

Aguiar

Figueiredo

2005

Analog Integr Circ Sig Process

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This paper discusses the design and performance of all-digital clock and data recovery mechanisms integrated in low-cost PLDs. Two designs have been explored and analyzed, using data sampling systems with phase detection and decision logic to select either the most appropriate sample as the recovered data or the most appropriate phase as the recovered clock. These mechanisms have been implemented in low cost PLDs from two major manufacturers. These PLDs have been further heavily loaded with typical communications functions, and the performance of the clock/data recovery circuits has been analyzed. The results show that different architectures behave differently, and that internal noise can significantly impair the performance of the circuit for high operating frequencies. This poses large difficulties to the re-usage of these blocks as generic virtual components. Nevertheless their overall performance typically exceeds regular telecommunications requirements.

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Section: B Phase-picking Algorithm and Implementationmentioning

confidence: 99%

Design and Performance of 155 Mbps Clock/Data Recovery Circuits on Heavy Loaded PLDs

Aguiar

Figueiredo

2005

Analog Integr Circ Sig Process

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“…• Both Dynamic Voltage Scaling (DVS) and Dynamic Frequency Scaling (DFS) computations decrease power usage fluctuating an utilitarian trademark: voltage or frequency, independently [16][17][18][19][20][21].…”

Section: The Power Utilization and Optimization Of Nodementioning

confidence: 99%

Low Power Wireless Sensor Networks Designing Aspects

J.Albarakati¹

2015

CAE

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The nodes are low powered devices and therefore illustrating a low power Wireless Sensor Networks (WSN) are exceptionally basic for getting longer lifetime in Wireless Sensor Networks. Here we are going to discuss operations of low power WSN and have also looked out for and discriminatingly examined particular setup or design issues, for instance, Power management, ultra-low power node arrangement, medium access control and duty cycle errands.

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“…But simultaneously they highlight that clock gating on FPGAs could have a much higher power saving efficiency if it would be possible to completely gate the FPGA clock tree. To overcome this drawback in [7] the authors provide an architectural block that is able to perform DFS. However, this approach leads to low-speed designs and clock skew problems as it is necessary to insert user logic into the clock network.…”

Section: Related Workmentioning

confidence: 99%

“…In general, the reconfiguration time for a different Virtex-II family device is given by t DCM ∼ frame length Byte * 2 67. 7 Byte/μs + frame length Byte * 4 90. 5 Byte/μs (@ICAP CLK = 100 MHz).…”

Section: Dcm Reconfiguration Details During Reconfiguration Ofmentioning

confidence: 99%

Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs

Schuck

Haetzer

Becker

2011

International Journal of Reconfigurable Computing

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Xilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous global clock nets to support high-speed mixed frequency designs. Digital Clock Managers in combination with Global Clock Buffers are already in place to generate the desired frequency and to drive the clock networks with different sources, respectively. Currently, almost all designs run at a fixed clock frequency determined statically during design time. Such systems cannot take the full advantage of partial and dynamic self-reconfiguration. Therefore, we introduce a new methodology that allows the implemented hardware to dynamically self-adopt the clock frequency during runtime by reconfiguring the Digital Clock Managers. We also present a method for online speed monitoring which is based on a two-dimensional online routing. The created speed maps of the FPGA area can be used as an input for the dynamic frequency scaling. Figures for reconfiguration performance and power savings are given. Further, the tradeoffs for reconfiguration effort using this method are evaluated. Results show the high potential and importance of the distributed dynamic frequency scaling method with little additional overhead.

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Dynamic clock management for low power applications in FPGAs

Cited by 31 publications

References 9 publications

Design and Performance of 155 Mbps Clock/Data Recovery Circuits on Heavy Loaded PLDs

Design and Performance of 155 Mbps Clock/Data Recovery Circuits on Heavy Loaded PLDs

Low Power Wireless Sensor Networks Designing Aspects

Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs

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