Dynamic code duplication with vulnerability awareness for soft error detection on VLIW architectures

Abstract

Soft errors are becoming a critical concern in embedded system designs. Code duplication techniques have been proposed to increase the reliability in multi-issue embedded systems such as VLIW by exploiting empty slots for duplicated instructions. However, they increase code size, another important concern, and ignore vulnerability differences in instructions, causing unnecessary or inefficient protection when selecting instructions to be duplicated under constraints. In this article, we propose a compiler-assisted dynamic code duplication method to minimize the code size overhead, and present vulnerability-aware duplication algorithms to maximize the effectiveness of instruction duplication with least overheads for VLIW architecture. Our experimental results with SoarGen and Synopsys simulation environments demonstrate that our proposals can reduce the code size by up to 40% and detect more soft errors by up to 82% via fault injection experiments over benchmarks from DSPstone and Livermore Loops as compared to the previously proposed instruction duplication technique.

Selective Code Duplication for Soft Error Protection on VLIW Architectures

“…How-ever, complete duplication of all instructions can incur severe overhead in terms of energy and performance due to a large number of instructions. In order to reduce the overhead from software-only protections, Hu et al [19], Lee et al [20], and Sartor et al [31] proposed a VLIW scheduling algorithm by exploiting unused instruction slots with minimal hardware modules such as register queues and comparator. Their approaches can schedule the original instructions and its duplicated instructions with considering performance or energy boundary.…”

“…If they are not identical, it is defined as soft errors on the datapath. Note that we have modified ISA [20] to recognize whether an instruction is or not. If an instruction is not duplicated, our architecture skips the comparison process.…”

“…However, the reliability of VLIW architectures has received much attention since VLIW architectures are commonly employed in "safety-critical" embedded systems such as aerospace, automotive, and rail transport applications [18]. In order to improve the reliability of VLIW architectures, several compiler-assisted instruction duplication [19,20] have been proposed by using NOPs and additional code lines. However, all the instructions in applications cannot be duplicated without performance overhead even though the complication techniques use the existing NOPs.…”

Userspace Hypervisor Data Characterization in Virtualized Environment

“…Memory-based HA is also considered a part of the entire system's HA. Redundancy has been applied at different levels of granularity, such as the hardware, thread, and instruction levels [36]. SWIFT, a software-only fault-detection technique, duplicates a program's instructions, inserting explicit validation codes to compare the results of original instructions and their corresponding duplicates [37].…”

“…In order to direct the level of high reliability, PROFIT [39] adjusts the level of protection and performance at fine granularities based on SWIFT. However, SWIFT incurs unwanted performance overhead as the number of instructions can be easily doubled, mainly due to the full duplication of instructions [36].…”