Dynamic Critical Resistance: A Timing-Based Critical Resistance Model for Statistical Delay Testing of Nanometer ICs

Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs

“…The investigation of optimal fault detectability dependence on V DD gains attention due to test escapes minimization interest especially for low power designs employing dynamic voltage scaling [8]. Previous research [4], [9], [10] suggested testing at the highest voltage level, but have not shown whether testing at the highest voltage level would always yield optimal detectability. Consequently, the work reported here attempts to answer whether multi-V DD testing is required when a range of supply and threshold voltages is provided.…”

Multivoltage Aware Resistive Open Fault Model

“…After generating the discrete open resistance set (line 1), the procedure starts in the first part by fault simulating all fault locations (ROF s), test patterns (T P s) using V DD settings (V DDs) and open resistance values (ROs) to obtain the path delay information (P D) as shown in lines (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18). Once the delay values (P D) for fault free paths (∀RO = 0) and faulty paths (∀RO ∈ ROs) are obtained, the longest path delays at each V DD of long paths (LP D G (V DD)) considering (T P ∈ T P s G ) and of short paths (LP D S (V DD)) considering (T P ∈ T P s S ) are identified using the fault free path delay data P D (∀RO = 0) as shown in line [19][20][21][22].…”

“…Additionally, ROF detectability with V DD is presented in Table IV columns [5][6][7][8][9][10]. The open resistance detection threshold is presented for small delays in columns 5-7 and gross delay faults in columns 8-10.…”

“…Other factors affecting the behavior include: the location of a ROF within the interconnect [24]; the threshold voltage [7]; capacitance of driven gates [25]; and the technology used [17]. Each of the named factors affects the delay differently, therefore the delay-voltage dependency is likely to vary across fault locations and so questions whether assuming a fixed behavior for a fault is correct.…”

“…Therefore screening for such faults is important to reduce test escapes, infant mortality failures and reject rates. To optimize the screening and detection of resistive open faults (ROFs), testing methods employing multiple supply voltages have been investigated and proved to give good results [5], [6], [7], [8]. With the emergence of low power designs which utilize multiple supply voltage levels [9], multi-V DD -based methods are ow of critical concern for effective testing and diagnosis [10], [11], [12], [13], [14].…”